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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 02/27] target/alpha: Convert to CPUClass::tlb_fill
Date: Fri, 10 May 2019 08:19:19 -0700	[thread overview]
Message-ID: <20190510151944.22981-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/alpha/cpu.h        |  5 +++--
 target/alpha/cpu.c        |  5 ++---
 target/alpha/helper.c     | 30 +++++++++++++++++++++---------
 target/alpha/mem_helper.c | 16 ----------------
 4 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 63bf3618ff..cf09112b6a 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -475,8 +475,9 @@ void alpha_cpu_list(void);
    is returned if the signal was handled by the virtual CPU.  */
 int cpu_alpha_signal_handler(int host_signum, void *pinfo,
                              void *puc);
-int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
-                               int mmu_idx);
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr);
 void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
 void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
 
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index ad3588a44a..7c81be4111 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -225,9 +225,8 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
     cc->set_pc = alpha_cpu_set_pc;
     cc->gdb_read_register = alpha_cpu_gdb_read_register;
     cc->gdb_write_register = alpha_cpu_gdb_write_register;
-#ifdef CONFIG_USER_ONLY
-    cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
-#else
+    cc->tlb_fill = alpha_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
     cc->do_transaction_failed = alpha_cpu_do_transaction_failed;
     cc->do_unaligned_access = alpha_cpu_do_unaligned_access;
     cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 7201576aae..929a217455 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -104,14 +104,15 @@ void cpu_alpha_store_gr(CPUAlphaState *env, unsigned reg, uint64_t val)
 }
 
 #if defined(CONFIG_USER_ONLY)
-int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
-                               int rw, int mmu_idx)
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr)
 {
     AlphaCPU *cpu = ALPHA_CPU(cs);
 
     cs->exception_index = EXCP_MMFAULT;
     cpu->env.trap_arg0 = address;
-    return 1;
+    cpu_loop_exit_restore(cs, retaddr);
 }
 #else
 /* Returns the OSF/1 entMM failure indication, or -1 on success.  */
@@ -248,26 +249,37 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     return (fail >= 0 ? -1 : phys);
 }
 
-int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int size, int rw,
-                               int mmu_idx)
+bool alpha_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
+                        MMUAccessType access_type, int mmu_idx,
+                        bool probe, uintptr_t retaddr)
 {
     AlphaCPU *cpu = ALPHA_CPU(cs);
     CPUAlphaState *env = &cpu->env;
     target_ulong phys;
     int prot, fail;
 
-    fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
+    fail = get_physical_address(env, addr, 1 << access_type,
+                                mmu_idx, &phys, &prot);
     if (unlikely(fail >= 0)) {
+        if (probe) {
+            return false;
+        }
         cs->exception_index = EXCP_MMFAULT;
         env->trap_arg0 = addr;
         env->trap_arg1 = fail;
-        env->trap_arg2 = (rw == 2 ? -1 : rw);
-        return 1;
+        env->trap_arg2 = (access_type == MMU_INST_FETCH ? -1 : access_type);
+        cpu_loop_exit_restore(cs, retaddr);
     }
 
     tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
                  prot, mmu_idx, TARGET_PAGE_SIZE);
-    return 0;
+    return true;
+}
+
+void tlb_fill(CPUState *cs, target_ulong addr, int size,
+              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+    alpha_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
 }
 #endif /* USER_ONLY */
 
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 011bc73dca..934faa1d6f 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -62,20 +62,4 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
     env->error_code = 0;
     cpu_loop_exit_restore(cs, retaddr);
 }
-
-/* try to fill the TLB and return an exception if error. If retaddr is
-   NULL, it means that the function was called in C code (i.e. not
-   from generated code or from helper.c) */
-/* XXX: fix it to restore all registers */
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
-              MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
-    int ret;
-
-    ret = alpha_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
-    if (unlikely(ret != 0)) {
-        /* Exception index and error code are already set */
-        cpu_loop_exit_restore(cs, retaddr);
-    }
-}
 #endif /* CONFIG_USER_ONLY */
-- 
2.17.1



  parent reply	other threads:[~2019-05-10 15:21 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-10 15:19 [Qemu-devel] [PULL 00/27] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 01/27] " Richard Henderson
2019-05-10 15:19 ` Richard Henderson [this message]
2019-05-10 15:19 ` [Qemu-devel] [PULL 03/27] target/arm: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 04/27] target/cris: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 05/27] target/hppa: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 06/27] target/i386: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 07/27] target/lm32: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 08/27] target/m68k: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 09/27] target/microblaze: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 12/27] target/mips: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 13/27] target/moxie: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 14/27] target/nios2: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 15/27] target/openrisc: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 16/27] target/ppc: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 17/27] target/riscv: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 18/27] target/s390x: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 19/27] target/sh4: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 20/27] target/sparc: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 21/27] target/tilegx: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 22/27] target/tricore: " Richard Henderson
2021-01-27 19:47   ` Philippe Mathieu-Daudé
2019-05-10 15:19 ` [Qemu-devel] [PULL 23/27] target/unicore32: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 24/27] target/xtensa: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 26/27] tcg: Remove CPUClass::handle_mmu_fault Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host Richard Henderson
2019-05-10 17:44 ` [Qemu-devel] [PULL 00/27] tcg: Add CPUClass::tlb_fill Peter Maydell

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