From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>
Subject: [Qemu-devel] [PULL 04/27] target/cris: Convert to CPUClass::tlb_fill
Date: Fri, 10 May 2019 08:19:21 -0700 [thread overview]
Message-ID: <20190510151944.22981-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190510151944.22981-1-richard.henderson@linaro.org>
Remove dumping of cpu state. Remove logging of PC, as that
value is garbage until cpu_restore_state.
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/cris/cpu.h | 5 +--
target/cris/cpu.c | 5 ++-
target/cris/helper.c | 67 +++++++++++++++++++++++------------------
target/cris/op_helper.c | 28 -----------------
4 files changed, 42 insertions(+), 63 deletions(-)
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 0fbe771639..857de79e24 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -281,8 +281,9 @@ static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
return !!(env->pregs[PR_CCS] & U_FLAG);
}
-int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
- int mmu_idx);
+bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr);
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 75729bfdd5..4e5288ae80 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -269,9 +269,8 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
-#ifdef CONFIG_USER_ONLY
- cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
-#else
+ cc->tlb_fill = cris_cpu_tlb_fill;
+#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_cris_cpu;
#endif
diff --git a/target/cris/helper.c b/target/cris/helper.c
index 3939603c73..69464837c8 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -24,6 +24,7 @@
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
+#include "exec/helper-proto.h"
//#define CRIS_HELPER_DEBUG
@@ -53,15 +54,15 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
cris_cpu_do_interrupt(cs);
}
-int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
- int mmu_idx)
+bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
{
CRISCPU *cpu = CRIS_CPU(cs);
cs->exception_index = 0xaa;
cpu->env.pregs[PR_EDA] = address;
- cpu_dump_state(cs, stderr, 0);
- return 1;
+ cpu_loop_exit_restore(cs, retaddr);
}
#else /* !CONFIG_USER_ONLY */
@@ -76,33 +77,19 @@ static void cris_shift_ccs(CPUCRISState *env)
env->pregs[PR_CCS] = ccs;
}
-int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
- int mmu_idx)
+bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
+ MMUAccessType access_type, int mmu_idx,
+ bool probe, uintptr_t retaddr)
{
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
struct cris_mmu_result res;
int prot, miss;
- int r = -1;
target_ulong phy;
- qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
- __func__, address, env->pc, rw);
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
- rw, mmu_idx, 0);
- if (miss) {
- if (cs->exception_index == EXCP_BUSFAULT) {
- cpu_abort(cs,
- "CRIS: Illegal recursive bus fault."
- "addr=%" VADDR_PRIx " rw=%d\n",
- address, rw);
- }
-
- env->pregs[PR_EDA] = address;
- cs->exception_index = EXCP_BUSFAULT;
- env->fault_vector = res.bf_vec;
- r = 1;
- } else {
+ access_type, mmu_idx, 0);
+ if (likely(!miss)) {
/*
* Mask off the cache selection bit. The ETRAX busses do not
* see the top bit.
@@ -111,15 +98,35 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
prot = res.prot;
tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
- r = 0;
+ return true;
}
- if (r > 0) {
- qemu_log_mask(CPU_LOG_MMU,
- "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
- " pc=%x\n", __func__, r, cs->interrupt_request, address,
- res.phy, res.bf_vec, env->pc);
+
+ if (probe) {
+ return false;
}
- return r;
+
+ if (cs->exception_index == EXCP_BUSFAULT) {
+ cpu_abort(cs, "CRIS: Illegal recursive bus fault."
+ "addr=%" VADDR_PRIx " access_type=%d\n",
+ address, access_type);
+ }
+
+ env->pregs[PR_EDA] = address;
+ cs->exception_index = EXCP_BUSFAULT;
+ env->fault_vector = res.bf_vec;
+ if (retaddr) {
+ if (cpu_restore_state(cs, retaddr, true)) {
+ /* Evaluate flags after retranslation. */
+ helper_top_evaluate_flags(env);
+ }
+ }
+ cpu_loop_exit(cs);
+}
+
+void tlb_fill(CPUState *cs, target_ulong addr, int size,
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+ cris_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr);
}
void crisv10_cpu_do_interrupt(CPUState *cs)
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 0ee3a3117b..26a395b413 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -37,34 +37,6 @@
#define D_LOG(...) do { } while (0)
#endif
-#if !defined(CONFIG_USER_ONLY)
-/* Try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
- CRISCPU *cpu = CRIS_CPU(cs);
- CPUCRISState *env = &cpu->env;
- int ret;
-
- D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
- env->pc, env->pregs[PR_EDA], (void *)retaddr);
- ret = cris_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
- if (unlikely(ret)) {
- if (retaddr) {
- /* now we have a real cpu fault */
- if (cpu_restore_state(cs, retaddr, true)) {
- /* Evaluate flags after retranslation. */
- helper_top_evaluate_flags(env);
- }
- }
- cpu_loop_exit(cs);
- }
-}
-
-#endif
-
void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
CPUState *cs = CPU(cris_env_get_cpu(env));
--
2.17.1
next prev parent reply other threads:[~2019-05-10 15:25 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-10 15:19 [Qemu-devel] [PULL 00/27] tcg: Add CPUClass::tlb_fill Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 01/27] " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 02/27] target/alpha: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 03/27] target/arm: " Richard Henderson
2019-05-10 15:19 ` Richard Henderson [this message]
2019-05-10 15:19 ` [Qemu-devel] [PULL 05/27] target/hppa: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 06/27] target/i386: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 07/27] target/lm32: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 08/27] target/m68k: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 09/27] target/microblaze: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 11/27] target/mips: Tidy control flow in mips_cpu_handle_mmu_fault Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 12/27] target/mips: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 13/27] target/moxie: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 14/27] target/nios2: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 15/27] target/openrisc: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 16/27] target/ppc: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 17/27] target/riscv: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 18/27] target/s390x: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 19/27] target/sh4: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 20/27] target/sparc: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 21/27] target/tilegx: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 22/27] target/tricore: " Richard Henderson
2021-01-27 19:47 ` Philippe Mathieu-Daudé
2019-05-10 15:19 ` [Qemu-devel] [PULL 23/27] target/unicore32: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 24/27] target/xtensa: " Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 25/27] tcg: Use CPUClass::tlb_fill in cputlb.c Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 26/27] tcg: Remove CPUClass::handle_mmu_fault Richard Henderson
2019-05-10 15:19 ` [Qemu-devel] [PULL 27/27] tcg: Use tlb_fill probe from tlb_vaddr_to_host Richard Henderson
2019-05-10 17:44 ` [Qemu-devel] [PULL 00/27] tcg: Add CPUClass::tlb_fill Peter Maydell
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