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[2001:470:27:1fa::2]) by smtp.gmail.com with ESMTPSA id 78sm4011lje.81.2019.05.14.13.45.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 May 2019 13:45:06 -0700 (PDT) From: Max Filippov To: qemu-devel@nongnu.org Date: Tue, 14 May 2019 13:44:38 -0700 Message-Id: <20190514204447.17486-1-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.11.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::242 Subject: [Qemu-devel] [PATCH 0/9] target/xtensa: implement options for modern cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Max Filippov Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hello, this series implements options used by the modern xtensa cores: memory protection unit, block prefetch and exclusive access and adds special register definitions and IRQ types for a few other options not fully implemented: ECC/parity, scatter/gather and IDMA. Max Filippov (9): target/xtensa: get rid of centralized SR properties target/xtensa: make internal MMU functions static target/xtensa: define IDMA and gather/scatter IRQ types target/xtensa: add parity/ECC option SRs target/xtensa: implement MPU option target/xtensa: implement DIWBUI.P opcode target/xtensa: implement block prefetch option opcodes target/xtensa: update list of exception causes target/xtensa: implement exclusive access option target/xtensa/cpu.c | 2 +- target/xtensa/cpu.h | 58 +- target/xtensa/helper.c | 1 + target/xtensa/helper.h | 6 + target/xtensa/mmu_helper.c | 532 ++++++- target/xtensa/op_helper.c | 42 + target/xtensa/overlay_tool.h | 43 +- target/xtensa/translate.c | 2951 ++++++++++++++++++++++++------------- tests/tcg/xtensa/test_exclusive.S | 48 + 9 files changed, 2574 insertions(+), 1109 deletions(-) create mode 100644 tests/tcg/xtensa/test_exclusive.S -- 2.11.0