From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [Qemu-devel] [PATCH 4/9] target/xtensa: add parity/ECC option SRs
Date: Tue, 14 May 2019 13:44:42 -0700 [thread overview]
Message-ID: <20190514204447.17486-5-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20190514204447.17486-1-jcmvbkbc@gmail.com>
Add SRs and rsr/wsr/xsr opcodes defined by the parity/ECC xtensa option.
The implementation is trivial since we don't emulate parity/ECC yet.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
target/xtensa/cpu.h | 6 ++
target/xtensa/overlay_tool.h | 2 +
target/xtensa/translate.c | 162 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 170 insertions(+)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d4258fcc6199..74ee7d125360 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -144,6 +144,12 @@ enum {
CACHEATTR = 98,
ATOMCTL = 99,
DDR = 104,
+ MEPC = 106,
+ MEPS = 107,
+ MESAVE = 108,
+ MESR = 109,
+ MECR = 110,
+ MEVADDR = 111,
IBREAKA = 128,
DBREAKA = 144,
DBREAKC = 160,
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index 8b380ce5e329..ffaab4b094cc 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -112,6 +112,8 @@
XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
+ XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
+ XTENSA_OPTION_MEMORY_ECC_PARITY) | \
/* Memory protection and translation */ \
XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
XTENSA_OPTION_REGION_PROTECTION) | \
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 100d6e126590..63a90fdd17dc 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -4216,6 +4216,60 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){MEMCTL},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "rsr.mecr",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MECR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rsr.mepc",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MEPC,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rsr.meps",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MEPS,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rsr.mesave",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESAVE,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rsr.mesr",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rsr.mevaddr",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "rsr.misc0",
.translate = translate_rsr,
.test_ill = test_ill_sr,
@@ -5036,6 +5090,60 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){MEMCTL},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "wsr.mecr",
+ .translate = translate_wsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MECR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "wsr.mepc",
+ .translate = translate_wsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MEPC,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "wsr.meps",
+ .translate = translate_wsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MEPS,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "wsr.mesave",
+ .translate = translate_wsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESAVE,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "wsr.mesr",
+ .translate = translate_wsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "wsr.mevaddr",
+ .translate = translate_wsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "wsr.misc0",
.translate = translate_wsr,
.test_ill = test_ill_sr,
@@ -5702,6 +5810,60 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){MEMCTL},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "xsr.mecr",
+ .translate = translate_xsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MECR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "xsr.mepc",
+ .translate = translate_xsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MEPC,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "xsr.meps",
+ .translate = translate_xsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MEPS,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "xsr.mesave",
+ .translate = translate_xsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESAVE,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "xsr.mesr",
+ .translate = translate_xsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "xsr.mevaddr",
+ .translate = translate_xsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MESR,
+ XTENSA_OPTION_MEMORY_ECC_PARITY,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "xsr.misc0",
.translate = translate_xsr,
.test_ill = test_ill_sr,
--
2.11.0
next prev parent reply other threads:[~2019-05-14 21:09 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-14 20:44 [Qemu-devel] [PATCH 0/9] target/xtensa: implement options for modern cores Max Filippov
2019-05-14 20:44 ` [Qemu-devel] [PATCH 1/9] target/xtensa: get rid of centralized SR properties Max Filippov
2019-05-14 20:44 ` [Qemu-devel] [PATCH 2/9] target/xtensa: make internal MMU functions static Max Filippov
2019-05-14 20:44 ` [Qemu-devel] [PATCH 3/9] target/xtensa: define IDMA and gather/scatter IRQ types Max Filippov
2019-05-14 20:44 ` Max Filippov [this message]
2019-05-14 20:44 ` [Qemu-devel] [PATCH 5/9] target/xtensa: implement MPU option Max Filippov
2019-05-14 20:44 ` [Qemu-devel] [PATCH 6/9] target/xtensa: implement DIWBUI.P opcode Max Filippov
2019-05-14 20:44 ` [Qemu-devel] [PATCH 7/9] target/xtensa: implement block prefetch option opcodes Max Filippov
2019-05-15 6:46 ` Philippe Mathieu-Daudé
2019-05-14 20:44 ` [Qemu-devel] [PATCH 8/9] target/xtensa: update list of exception causes Max Filippov
2019-05-14 20:44 ` [Qemu-devel] [PATCH 9/9] target/xtensa: implement exclusive access option Max Filippov
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