From: "Daniel P. Berrangé" <berrange@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 2/2] docs: recommend use of md-clear feature on all Intel CPUs
Date: Wed, 15 May 2019 15:10:11 +0100 [thread overview]
Message-ID: <20190515141011.5315-3-berrange@redhat.com> (raw)
In-Reply-To: <20190515141011.5315-1-berrange@redhat.com>
Update x86 CPU model guidance to recommend that the md-clear feature is
manually enabled with all Intel CPU models, when supported by the host
microcode.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
docs/qemu-cpu-models.texi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/docs/qemu-cpu-models.texi b/docs/qemu-cpu-models.texi
index 23c11dc86f..ad040cfc98 100644
--- a/docs/qemu-cpu-models.texi
+++ b/docs/qemu-cpu-models.texi
@@ -200,6 +200,18 @@ Not included by default in any Intel CPU model.
Should be explicitly turned on for all Intel CPU models.
Note that not all CPU hardware will support this feature.
+
+@item @code{md-clear}
+
+Required to confirm the MDS (CVE-2018-12126, CVE-2018-12127, CVE-2018-12130,
+CVE-2019-11091) fixes.
+
+Not included by default in any Intel CPU model.
+
+Must be explicitly turned on for all Intel CPU models.
+
+Requires the host CPU microcode to support this feature before it
+can be used for guest CPUs.
@end table
--
2.21.0
prev parent reply other threads:[~2019-05-15 14:13 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-15 14:10 [Qemu-devel] [PATCH 0/2] x86/cpu: add "md-clear" feature for MDS security flaws Daniel P. Berrangé
2019-05-15 14:10 ` [Qemu-devel] [PATCH 1/2] target/i386: define md-clear bit Daniel P. Berrangé
2019-05-15 14:10 ` Daniel P. Berrangé [this message]
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