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[97.113.13.231]) by smtp.gmail.com with ESMTPSA id 132sm7709625pga.79.2019.05.16.21.51.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 May 2019 21:51:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 16 May 2019 21:51:23 -0700 Message-Id: <20190517045136.3509-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::632 Subject: [Qemu-devel] [PATCH v14 00/13] RX architecture support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, ysato@users.sourceforge.jp Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is Sato-san's v13, plus the typos that Phil noticed therein, plus the change to tlb_fill required by commit d8276573da58e8ce78dab8c46dd660efd664bcb7 Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' Add CPUClass::tlb_fill. Improve tlb_vaddr_to_host for use by ARM SVE no-fault loads. r~ Richard Henderson (1): target/rx: Convert to CPUClass::tlb_fill Yoshinori Sato (12): target/rx: TCG translation target/rx: TCG helper target/rx: CPU definition target/rx: RX disassembler hw/intc: RX62N interrupt controller (ICUa) hw/timer: RX62N internal timer modules hw/char: RX62N serial communication interface (SCI) hw/rx: RX Target hardware definition qemu/bitops.h: Add extract8 and extract16 hw/registerfields.h: Add 8bit and 16bit register macros Add rx-softmmu MAINTAINERS: Add RX include/disas/dis-asm.h | 5 + include/hw/char/renesas_sci.h | 45 + include/hw/intc/rx_icu.h | 56 + include/hw/registerfields.h | 32 +- include/hw/rx/rx.h | 7 + include/hw/rx/rx62n.h | 94 ++ include/hw/timer/renesas_cmt.h | 38 + include/hw/timer/renesas_tmr.h | 53 + include/qemu/bitops.h | 38 + include/sysemu/arch_init.h | 1 + target/rx/cpu.h | 227 +++ target/rx/helper.h | 31 + arch_init.c | 2 + hw/char/renesas_sci.c | 340 +++++ hw/intc/rx_icu.c | 376 +++++ hw/rx/rx-virt.c | 105 ++ hw/rx/rx62n.c | 238 ++++ hw/timer/renesas_cmt.c | 275 ++++ hw/timer/renesas_tmr.c | 455 ++++++ target/rx/cpu.c | 236 ++++ target/rx/disas.c | 1480 +++++++++++++++++++ target/rx/gdbstub.c | 112 ++ target/rx/helper.c | 148 ++ target/rx/monitor.c | 38 + target/rx/op_helper.c | 470 ++++++ target/rx/translate.c | 2432 ++++++++++++++++++++++++++++++++ MAINTAINERS | 19 + configure | 8 + default-configs/rx-softmmu.mak | 3 + hw/Kconfig | 1 + hw/char/Kconfig | 3 + hw/char/Makefile.objs | 1 + hw/intc/Kconfig | 3 + hw/intc/Makefile.objs | 1 + hw/rx/Kconfig | 14 + hw/rx/Makefile.objs | 2 + hw/timer/Kconfig | 6 + hw/timer/Makefile.objs | 3 + target/rx/Makefile.objs | 12 + target/rx/insns.decode | 621 ++++++++ 40 files changed, 8030 insertions(+), 1 deletion(-) create mode 100644 include/hw/char/renesas_sci.h create mode 100644 include/hw/intc/rx_icu.h create mode 100644 include/hw/rx/rx.h create mode 100644 include/hw/rx/rx62n.h create mode 100644 include/hw/timer/renesas_cmt.h create mode 100644 include/hw/timer/renesas_tmr.h create mode 100644 target/rx/cpu.h create mode 100644 target/rx/helper.h create mode 100644 hw/char/renesas_sci.c create mode 100644 hw/intc/rx_icu.c create mode 100644 hw/rx/rx-virt.c create mode 100644 hw/rx/rx62n.c create mode 100644 hw/timer/renesas_cmt.c create mode 100644 hw/timer/renesas_tmr.c create mode 100644 target/rx/cpu.c create mode 100644 target/rx/disas.c create mode 100644 target/rx/gdbstub.c create mode 100644 target/rx/helper.c create mode 100644 target/rx/monitor.c create mode 100644 target/rx/op_helper.c create mode 100644 target/rx/translate.c create mode 100644 default-configs/rx-softmmu.mak create mode 100644 hw/rx/Kconfig create mode 100644 hw/rx/Makefile.objs create mode 100644 target/rx/Makefile.objs create mode 100644 target/rx/insns.decode -- 2.17.1