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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y18sm5418641wmd.29.2019.05.17.10.40.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 May 2019 10:40:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 17 May 2019 18:40:42 +0100 Message-Id: <20190517174046.11146-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [PATCH 0/4] Disable FPU/DSP for CPU0 on musca-a and mps2-an521 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The SSE-200 hardware has configurable integration settings which determine whether its two CPUs have the FPU and DSP: * CPU0_FPU (default 0) * CPU0_DSP (default 0) * CPU1_FPU (default 1) * CPU1_DSP (default 1) Similarly, the IoTKit has settings for its single CPU: * CPU0_FPU (default 1) * CPU0_DSP (default 1) Of our four boards that use either the IoTKit or the SSE-200: * mps2-an505, mps2-an521 and musca-a use the default settings * musca-b1 enables FPU and DSP on both CPUs Currently QEMU models all these boards using CPUs with both FPU and DSP enabled. This means that we are incorrect for mps2-an521 and musca-a, which should not have FPU or DSP on CPU0. This patchset fixes this (fairly minor) inaccuracy by implementing properties on the CPU to disable the relevant CPU features and then wiring them up through the armv7m object and the ARMSSE SoC container object, so that our IotKit and SSE200 models behave by default the same way as the hardware default does, and our Musca-B1 board model forces the FPU/DSP to be present on CPU, as the hardware does. The 'neon' property is not strictly required for the M-profile issues described above, but I implemented it on the CPU object because disable-neon and disable-vfp interact for A-profile CPUs. thanks -- PMM Peter Maydell (4): target/arm: Allow VFP and Neon to be disabled via a CPU property target/arm: Allow M-profile CPUs to disable the DSP extension via CPU property hw/arm/armv7m: Forward "vfp" and "dsp" properties to CPU hw/arm: Correctly disable FPU/DSP for some ARMSSE-based boards include/hw/arm/armsse.h | 7 ++ include/hw/arm/armv7m.h | 4 + target/arm/cpu.h | 6 ++ hw/arm/armsse.c | 58 ++++++++++--- hw/arm/armv7m.c | 18 ++++ hw/arm/musca.c | 8 ++ target/arm/cpu.c | 179 ++++++++++++++++++++++++++++++++++++++-- 7 files changed, 262 insertions(+), 18 deletions(-) -- 2.20.1