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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@redhat.com, ysato@users.sourceforge.jp
Subject: [Qemu-devel] [PATCH v16 10/23] hw/registerfields.h: Add 8bit and 16bit register macros
Date: Fri, 31 May 2019 08:43:02 -0500	[thread overview]
Message-ID: <20190531134315.4109-11-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190531134315.4109-1-richard.henderson@linaro.org>

From: Yoshinori Sato <ysato@users.sourceforge.jp>

Some RX peripheral using 8bit and 16bit registers.
Added 8bit and 16bit APIs.

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190516055244.95559-11-ysato@users.sourceforge.jp>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/registerfields.h | 32 +++++++++++++++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h
index 2659a58737..a0bb0654d6 100644
--- a/include/hw/registerfields.h
+++ b/include/hw/registerfields.h
@@ -22,6 +22,14 @@
     enum { A_ ## reg = (addr) };                                          \
     enum { R_ ## reg = (addr) / 4 };
 
+#define REG8(reg, addr)                                                  \
+    enum { A_ ## reg = (addr) };                                          \
+    enum { R_ ## reg = (addr) };
+
+#define REG16(reg, addr)                                                  \
+    enum { A_ ## reg = (addr) };                                          \
+    enum { R_ ## reg = (addr) / 2 };
+
 /* Define SHIFT, LENGTH and MASK constants for a field within a register */
 
 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LENGTH
@@ -34,6 +42,12 @@
                                         MAKE_64BIT_MASK(shift, length)};
 
 /* Extract a field from a register */
+#define FIELD_EX8(storage, reg, field)                                    \
+    extract8((storage), R_ ## reg ## _ ## field ## _SHIFT,                \
+              R_ ## reg ## _ ## field ## _LENGTH)
+#define FIELD_EX16(storage, reg, field)                                   \
+    extract16((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
+              R_ ## reg ## _ ## field ## _LENGTH)
 #define FIELD_EX32(storage, reg, field)                                   \
     extract32((storage), R_ ## reg ## _ ## field ## _SHIFT,               \
               R_ ## reg ## _ ## field ## _LENGTH)
@@ -49,6 +63,22 @@
  * Assigning values larger then the target field will result in
  * compilation warnings.
  */
+#define FIELD_DP8(storage, reg, field, val) ({                            \
+    struct {                                                              \
+        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
+    } v = { .v = val };                                                   \
+    uint8_t d;                                                            \
+    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
+                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
+    d; })
+#define FIELD_DP16(storage, reg, field, val) ({                           \
+    struct {                                                              \
+        unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
+    } v = { .v = val };                                                   \
+    uint16_t d;                                                           \
+    d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
+                  R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
+    d; })
 #define FIELD_DP32(storage, reg, field, val) ({                           \
     struct {                                                              \
         unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
@@ -57,7 +87,7 @@
     d = deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT,           \
                   R_ ## reg ## _ ## field ## _LENGTH, v.v);               \
     d; })
-#define FIELD_DP64(storage, reg, field, val) ({                           \
+#define FIELD_DP64(storage, reg, field, val) ({                         \
     struct {                                                              \
         unsigned int v:R_ ## reg ## _ ## field ## _LENGTH;                \
     } v = { .v = val };                                                   \
-- 
2.17.1



  parent reply	other threads:[~2019-05-31 13:56 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-31 13:42 [Qemu-devel] [PATCH v16 00/23] Add RX architecture Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 01/23] target/rx: TCG translation Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 02/23] target/rx: TCG helper Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 03/23] target/rx: CPU definition Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 04/23] target/rx: RX disassembler Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 05/23] hw/intc: RX62N interrupt controller (ICUa) Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 06/23] hw/timer: RX62N internal timer modules Richard Henderson
2019-05-31 13:42 ` [Qemu-devel] [PATCH v16 07/23] hw/char: RX62N serial communication interface (SCI) Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 08/23] hw/rx: RX Target hardware definition Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 09/23] qemu/bitops.h: Add extract8 and extract16 Richard Henderson
2019-05-31 13:43 ` Richard Henderson [this message]
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 11/23] target/rx: Convert to CPUClass::tlb_fill Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 12/23] target/rx: Add RX to SysEmuTarget Richard Henderson
2019-06-04  5:32   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 13/23] target/rx: Fix cpu types and names Richard Henderson
2019-05-31 14:23   ` Igor Mammedov
2019-05-31 14:59     ` Richard Henderson
2019-05-31 15:15       ` Igor Mammedov
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 14/23] tests: Add rx to machine-none-test.c Richard Henderson
2019-06-04  5:33   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 15/23] hw/rx: Honor -accel qtest Richard Henderson
2019-06-04  5:34   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 16/23] Add rx-softmmu Richard Henderson
2019-06-04  6:38   ` Philippe Mathieu-Daudé
2019-06-04 14:25     ` Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 17/23] MAINTAINERS: Add RX Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 18/23] target/rx: Disassemble rx_index_addr into a string Richard Henderson
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 19/23] target/rx: Replace operand with prt_ldmi in disassembler Richard Henderson
2019-06-04  5:37   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 20/23] target/rx: Use prt_ldmi for XCHG_mr disassembly Richard Henderson
2019-06-04  5:38   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 21/23] target/rx: Emit all disassembly in one prt() Richard Henderson
2019-06-04  5:36   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 22/23] target/rx: Collect all bytes during disassembly Richard Henderson
2019-06-04  5:41   ` Philippe Mathieu-Daudé
2019-05-31 13:43 ` [Qemu-devel] [PATCH v16 23/23] target/rx: Dump bytes for each insn " Richard Henderson
2019-06-04  5:35   ` Philippe Mathieu-Daudé
2019-05-31 14:12 ` [Qemu-devel] [PATCH v16 00/23] Add RX architecture no-reply
2019-06-04  5:23 ` Philippe Mathieu-Daudé

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