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From: David Hildenbrand <david@redhat.com>
To: qemu-devel@nongnu.org
Cc: Thomas Huth <thuth@redhat.com>,
	Denys Vlasenko <dvlasenk@redhat.com>,
	David Hildenbrand <david@redhat.com>,
	Cornelia Huck <cohuck@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Pino Toscano <ptoscano@redhat.com>,
	Christian Borntraeger <borntraeger@de.ibm.com>,
	qemu-s390x@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 07/22] s390x/tcg: Implement VECTOR FP CONVERT FROM FIXED 64-BIT
Date: Mon,  3 Jun 2019 11:06:20 +0200	[thread overview]
Message-ID: <20190603090635.10631-8-david@redhat.com> (raw)
In-Reply-To: <20190603090635.10631-1-david@redhat.com>

1. We'll reuse op_vcdg() for similar instructions later, prepare for
   that.
2. We'll reuse vop64_2() later for other instructions.

We have to mangle the erm (effective rounding mode) and the m4 into
the simd_data(), and properly unmangle them again.

Make sure to restore the erm before triggering an exception.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
 target/s390x/helper.h           |  2 ++
 target/s390x/insn-data.def      |  2 ++
 target/s390x/translate_vx.inc.c | 25 ++++++++++++++++++
 target/s390x/vec_fpu_helper.c   | 47 +++++++++++++++++++++++++++++++++
 4 files changed, 76 insertions(+)

diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 33d3bacf74..a60f4c49fc 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -266,6 +266,8 @@ DEF_HELPER_FLAGS_5(gvec_vfche64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32
 DEF_HELPER_FLAGS_5(gvec_vfche64s, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
 DEF_HELPER_5(gvec_vfche64_cc, void, ptr, cptr, cptr, env, i32)
 DEF_HELPER_5(gvec_vfche64s_cc, void, ptr, cptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdg64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vcdg64s, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
 
 #ifndef CONFIG_USER_ONLY
 DEF_HELPER_3(servc, i32, env, i64, i64)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 446552f251..d3386024c8 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1218,6 +1218,8 @@
     F(0xe7eb, VFCH,    VRR_c, V,   0, 0, 0, 0, vfc, 0, IF_VEC)
 /* VECTOR FP COMPARE HIGH OR EQUAL */
     F(0xe7ea, VFCHE,   VRR_c, V,   0, 0, 0, 0, vfc, 0, IF_VEC)
+/* VECTOR FP CONVERT FROM FIXED 64-BIT */
+    F(0xe7c3, VCDG,    VRR_a, V,   0, 0, 0, 0, vcdg, 0, IF_VEC)
 
 #ifndef CONFIG_USER_ONLY
 /* COMPARE AND SWAP AND PURGE */
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 5571a71e1a..6741b707cc 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -2639,3 +2639,28 @@ static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
     }
     return DISAS_NEXT;
 }
+
+static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
+{
+    const uint8_t fpf = get_field(s->fields, m3);
+    const uint8_t m4 = get_field(s->fields, m4);
+    const uint8_t erm = get_field(s->fields, m5);
+    const bool se = extract32(m4, 3, 1);
+    gen_helper_gvec_2_ptr *fn;
+
+    if (fpf != FPF_LONG || extract32(m4, 0, 2) || erm > 7 || erm == 2) {
+        gen_program_exception(s, PGM_SPECIFICATION);
+        return DISAS_NORETURN;
+    }
+
+    switch (s->fields->op2) {
+    case 0xc3:
+        fn = se ? gen_helper_gvec_vcdg64s : gen_helper_gvec_vcdg64;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+    gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+                   deposit32(m4, 4, 4, erm), fn);
+    return DISAS_NEXT;
+}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index e72500d4d5..53430c7843 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -78,6 +78,30 @@ static void handle_ieee_exc(CPUS390XState *env, uint8_t vxc, uint8_t vec_exc,
     }
 }
 
+typedef uint64_t (*vop64_2_fn)(uint64_t a, float_status *s);
+static void vop64_2(S390Vector *v1, const S390Vector *v2, CPUS390XState *env,
+                    bool s, bool XxC, uint8_t erm, vop64_2_fn fn,
+                    uintptr_t retaddr)
+{
+    uint8_t vxc, vec_exc = 0;
+    S390Vector tmp = {};
+    int i, old_mode;
+
+    old_mode = s390_swap_bfp_rounding_mode(env, erm);
+    for (i = 0; i < 2; i++) {
+        const uint64_t a = s390_vec_read_element64(v2, i);
+
+        s390_vec_write_element64(&tmp, i, fn(a, &env->fpu_status));
+        vxc = check_ieee_exc(env, i, XxC, &vec_exc);
+        if (s || vxc) {
+            break;
+        }
+    }
+    s390_restore_bfp_rounding_mode(env, old_mode);
+    handle_ieee_exc(env, vxc, vec_exc, retaddr);
+    *v1 = tmp;
+}
+
 typedef uint64_t (*vop64_3_fn)(uint64_t a, uint64_t b, float_status *s);
 static void vop64_3(S390Vector *v1, const S390Vector *v2, const S390Vector *v3,
                     CPUS390XState *env, bool s, vop64_3_fn fn,
@@ -253,3 +277,26 @@ void HELPER(gvec_vfche64s_cc)(void *v1, const void *v2, const void *v3,
 {
     env->cc_op = vfc64(v1, v2, v3, env, true, float64_le_quiet, GETPC());
 }
+
+static uint64_t vcdg64(uint64_t a, float_status *s)
+{
+    return int64_to_float64(a, s);
+}
+
+void HELPER(gvec_vcdg64)(void *v1, const void *v2, CPUS390XState *env,
+                         uint32_t desc)
+{
+    const uint8_t erm = extract32(simd_data(desc), 4, 4);
+    const bool XxC = extract32(simd_data(desc), 2, 1);
+
+    vop64_2(v1, v2, env, false, XxC, erm, vcdg64, GETPC());
+}
+
+void HELPER(gvec_vcdg64s)(void *v1, const void *v2, CPUS390XState *env,
+                          uint32_t desc)
+{
+    const uint8_t erm = extract32(simd_data(desc), 4, 4);
+    const bool XxC = extract32(simd_data(desc), 2, 1);
+
+    vop64_2(v1, v2, env, true, XxC, erm, vcdg64, GETPC());
+}
-- 
2.21.0



  parent reply	other threads:[~2019-06-03  9:11 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-03  9:06 [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 01/22] s390x/tcg: Store only the necessary amount of doublewords for STFLE David Hildenbrand
2019-06-03  9:07   ` David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 02/22] s390x/tcg: Introduce tcg_s390_vector_exception() David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 03/22] s390x/tcg: Export float_comp_to_cc() and float(32|64|128)_dcmask() David Hildenbrand
2019-06-03 16:17   ` Richard Henderson
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 04/22] s390x/tcg: Implement VECTOR FP ADD David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 05/22] s390x/tcg: Implement VECTOR FP COMPARE (AND SIGNAL) SCALAR David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 06/22] s390x/tcg: Implement VECTOR FP COMPARE (EQUAL|HIGH|HIGH OR EQUAL) David Hildenbrand
2019-06-05  9:19   ` David Hildenbrand
2019-06-05 14:47     ` Richard Henderson
2019-06-03  9:06 ` David Hildenbrand [this message]
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 08/22] s390x/tcg: Implement VECTOR FP CONVERT FROM LOGICAL 64-BIT David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 09/22] s390x/tcg: Implement VECTOR FP CONVERT TO FIXED 64-BIT David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 10/22] s390x/tcg: Implement VECTOR FP CONVERT TO LOGICAL 64-BIT David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 11/22] s390x/tcg: Implement VECTOR FP DIVIDE David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 12/22] s390x/tcg: Implement VECTOR LOAD FP INTEGER David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 13/22] s390x/tcg: Implement VECTOR LOAD LENGTHENED David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 14/22] s390x/tcg: Implement VECTOR LOAD ROUNDED David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 15/22] s390x/tcg: Implement VECTOR FP MULTIPLY David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 16/22] s390x/tcg: Implement VECTOR FP MULTIPLY AND (ADD|SUBTRACT) David Hildenbrand
2019-06-03 16:16   ` Richard Henderson
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 17/22] s390x/tcg: Implement VECTOR FP PERFORM SIGN OPERATION David Hildenbrand
2019-06-03 16:18   ` Richard Henderson
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 18/22] s390x/tcg: Implement VECTOR FP SQUARE ROOT David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 19/22] s390x/tcg: Implement VECTOR FP SUBTRACT David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 20/22] s390x/tcg: Implement VECTOR FP TEST DATA CLASS IMMEDIATE David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 21/22] s390x/tcg: Allow linux-user to use vector instructions David Hildenbrand
2019-06-04  7:45   ` Laurent Vivier
2019-06-04  8:50   ` Laurent Vivier
2019-06-04  8:56     ` David Hildenbrand
2019-06-03  9:06 ` [Qemu-devel] [PATCH v2 22/22] s390x/tcg: We support the Vector Facility David Hildenbrand
2019-06-03  9:09 ` [Qemu-devel] [PATCH v2 00/22] s390x/tcg: Vector Instruction Support Part 4 David Hildenbrand
2019-06-03  9:17 ` [Qemu-devel] [PATCH v2 23/22] s390x: Bump the "qemu" CPU model up to a stripped-down z13 David Hildenbrand

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