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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Yoshinori Sato <ysato@users.sourceforge.jp>,
	qemu-devel@nongnu.org, Igor Mammedov <imammedo@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>
Cc: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [Qemu-devel] [PATCH v18 23/29] target/rx: Emit all disassembly in one prt()
Date: Fri,  7 Jun 2019 17:37:19 +0200	[thread overview]
Message-ID: <20190607153725.18055-24-philmd@redhat.com> (raw)
In-Reply-To: <20190607153725.18055-1-philmd@redhat.com>

From: Richard Henderson <richard.henderson@linaro.org>

Many of the multi-part prints have been eliminated by previous
patches.  Eliminate the rest of them.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20190607091116.49044-22-ysato@users.sourceforge.jp>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/rx/disas.c | 75 ++++++++++++++++++++++++-----------------------
 1 file changed, 39 insertions(+), 36 deletions(-)

diff --git a/target/rx/disas.c b/target/rx/disas.c
index db10385fd0..ebc1a44249 100644
--- a/target/rx/disas.c
+++ b/target/rx/disas.c
@@ -228,24 +228,21 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
 /* mov.[bwl] rs,rd */
 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
 {
-    char dspd[8], dsps[8];
+    char dspd[8], dsps[8], szc = size[a->sz];
 
-    prt("mov.%c\t", size[a->sz]);
     if (a->lds == 3 && a->ldd == 3) {
         /* mov.[bwl] rs,rd */
-        prt("r%d, r%d", a->rs, a->rd);
-        return true;
-    }
-    if (a->lds == 3) {
+        prt("mov.%c\tr%d, r%d", szc, a->rs, a->rd);
+    } else if (a->lds == 3) {
         rx_index_addr(ctx, dspd, a->ldd, a->sz);
-        prt("r%d, %s[r%d]", a->rs, dspd, a->rd);
+        prt("mov.%c\tr%d, %s[r%d]", szc, a->rs, dspd, a->rd);
     } else if (a->ldd == 3) {
         rx_index_addr(ctx, dsps, a->lds, a->sz);
-        prt("%s[r%d], r%d", dsps, a->rs, a->rd);
+        prt("mov.%c\t%s[r%d], r%d", szc, dsps, a->rs, a->rd);
     } else {
         rx_index_addr(ctx, dsps, a->lds, a->sz);
         rx_index_addr(ctx, dspd, a->ldd, a->sz);
-        prt("%s[r%d], %s[r%d]", dsps, a->rs, dspd, a->rd);
+        prt("mov.%c\t%s[r%d], %s[r%d]", szc, dsps, a->rs, dspd, a->rd);
     }
     return true;
 }
@@ -254,8 +251,11 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
 /* mov.[bwl] rs,[-rd] */
 static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
 {
-    prt("mov.%c\tr%d, ", size[a->sz], a->rs);
-    prt((a->ad == 0) ? "[r%d+]" : "[-r%d]", a->rd);
+    if (a->ad) {
+        prt("mov.%c\tr%d, [-r%d]", size[a->sz], a->rs, a->rd);
+    } else {
+        prt("mov.%c\tr%d, [r%d+]", size[a->sz], a->rs, a->rd);
+    }
     return true;
 }
 
@@ -263,9 +263,11 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
 /* mov.[bwl] [-rd],rs */
 static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a)
 {
-    prt("mov.%c\t", size[a->sz]);
-    prt((a->ad == 0) ? "[r%d+]" : "[-r%d]", a->rd);
-    prt(", r%d", a->rs);
+    if (a->ad) {
+        prt("mov.%c\t[-r%d], r%d", size[a->sz], a->rd, a->rs);
+    } else {
+        prt("mov.%c\t[r%d+], r%d", size[a->sz], a->rd, a->rs);
+    }
     return true;
 }
 
@@ -299,9 +301,11 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a)
 /* movu.[bw] [-rs],rd */
 static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a)
 {
-    prt("movu.%c\t", size[a->sz]);
-    prt((a->ad == 0) ? "[r%d+]" : "[-r%d]", a->rd);
-    prt(", r%d", a->rs);
+    if (a->ad) {
+        prt("movu.%c\t[-r%d], r%d", size[a->sz], a->rd, a->rs);
+    } else {
+        prt("movu.%c\t[r%d+], r%d", size[a->sz], a->rd, a->rs);
+    }
     return true;
 }
 
@@ -478,11 +482,11 @@ static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
 /* not rs, rd */
 static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
 {
-    prt("not\t");
     if (a->rs != a->rd) {
-        prt("r%d, ", a->rs);
+        prt("not\tr%d, r%d", a->rs, a->rd);
+    } else {
+        prt("not\tr%d", a->rs);
     }
-    prt("r%d", a->rd);
     return true;
 }
 
@@ -490,11 +494,11 @@ static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
 /* neg rs, rd */
 static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
 {
-    prt("neg\t");
     if (a->rs != a->rd) {
-        prt("r%d, ", a->rs);
+        prt("neg\tr%d, r%d", a->rs, a->rd);
+    } else {
+        prt("neg\tr%d", a->rs);
     }
-    prt("r%d", a->rd);
     return true;
 }
 
@@ -606,11 +610,10 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a)
 /* abs rs, rd */
 static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a)
 {
-    prt("abs\t");
-    if (a->rs == a->rd) {
-        prt("r%d", a->rd);
+    if (a->rs != a->rd) {
+        prt("abs\tr%d, r%d", a->rs, a->rd);
     } else {
-        prt("r%d, r%d", a->rs, a->rd);
+        prt("abs\tr%d", a->rs);
     }
     return true;
 }
@@ -733,11 +736,11 @@ static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
 /* shll #imm:5, rs, rd */
 static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a)
 {
-    prt("shll\t#%d, ", a->imm);
     if (a->rs2 != a->rd) {
-        prt("r%d, ", a->rs2);
+        prt("shll\t#%d, r%d, r%d", a->imm, a->rs2, a->rd);
+    } else {
+        prt("shll\t#%d, r%d", a->imm, a->rd);
     }
-    prt("r%d", a->rd);
     return true;
 }
 
@@ -752,11 +755,11 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
 /* shar #imm:5, rs, rd */
 static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a)
 {
-    prt("shar\t#%d,", a->imm);
     if (a->rs2 != a->rd) {
-        prt("r%d, ", a->rs2);
+        prt("shar\t#%d, r%d, r%d", a->imm, a->rs2, a->rd);
+    } else {
+        prt("shar\t#%d, r%d", a->imm, a->rd);
     }
-    prt("r%d", a->rd);
     return true;
 }
 
@@ -771,11 +774,11 @@ static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a)
 /* shlr #imm:5, rs, rd */
 static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a)
 {
-    prt("shlr\t#%d, ", a->imm);
     if (a->rs2 != a->rd) {
-        prt("r%d, ", a->rs2);
+        prt("shlr\t#%d, r%d, r%d", a->imm, a->rs2, a->rd);
+    } else {
+        prt("shlr\t#%d, r%d", a->imm, a->rd);
     }
-    prt("r%d", a->rd);
     return true;
 }
 
-- 
2.20.1



  parent reply	other threads:[~2019-06-07 16:53 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-07 15:36 [Qemu-devel] [PATCH v18 00/29] Add RX archtecture support Philippe Mathieu-Daudé
2019-06-07 15:36 ` [Qemu-devel] [PATCH v18 01/29] target/rx: TCG translation Philippe Mathieu-Daudé
2019-06-07 15:36 ` [Qemu-devel] [PATCH v18 02/29] target/rx: TCG helper Philippe Mathieu-Daudé
2019-06-07 15:36 ` [Qemu-devel] [PATCH v18 03/29] target/rx: CPU definition Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 04/29] !fixup " Philippe Mathieu-Daudé
2019-06-07 18:02   ` Eric Blake
2019-06-07 18:06     ` Philippe Mathieu-Daudé
2019-06-10 12:59       ` Igor Mammedov
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 05/29] " Philippe Mathieu-Daudé
2019-06-07 15:43   ` Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 06/29] target/rx: RX disassembler Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 07/29] hw/intc: RX62N interrupt controller (ICUa) Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 08/29] hw/timer: RX62N internal timer modules Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 09/29] hw/char: RX62N serial communication interface (SCI) Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 10/29] hw/rx: RX Target hardware definition Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 11/29] !fixup " Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 12/29] qemu/bitops.h: Add extract8 and extract16 Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 13/29] hw/registerfields.h: Add 8bit and 16bit register macros Philippe Mathieu-Daudé
2019-06-07 20:56   ` Alistair Francis
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 14/29] target/rx: Convert to CPUClass::tlb_fill Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 15/29] target/rx: Add RX to SysEmuTarget Philippe Mathieu-Daudé
2019-06-07 18:04   ` Eric Blake
2019-06-07 18:08     ` Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 16/29] tests: Add rx to machine-none-test.c Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 17/29] hw/rx: Honor -accel qtest Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 18/29] Add rx-softmmu Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 19/29] MAINTAINERS: Add RX Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 20/29] target/rx: Disassemble rx_index_addr into a string Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 21/29] target/rx: Replace operand with prt_ldmi in disassembler Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 22/29] target/rx: Use prt_ldmi for XCHG_mr disassembly Philippe Mathieu-Daudé
2019-06-07 15:37 ` Philippe Mathieu-Daudé [this message]
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 24/29] target/rx: Collect all bytes during disassembly Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 25/29] target/rx: Dump bytes for each insn " Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 26/29] target/rx: Restrict access to extable[] Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 27/29] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core Philippe Mathieu-Daudé
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 28/29] hw/rx: Fix comments Philippe Mathieu-Daudé
2019-06-07 16:57   ` Peter Maydell
2019-06-07 15:37 ` [Qemu-devel] [PATCH v18 29/29] BootLinuxConsoleTest: Test the RX-Virt machine Philippe Mathieu-Daudé
2019-06-08  0:50 ` [Qemu-devel] [PATCH v18 00/29] Add RX archtecture support no-reply
2019-06-10  6:03 ` Yoshinori Sato

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