From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 25/39] target/sh4: Use env_cpu, env_archcpu
Date: Sun, 9 Jun 2019 19:02:04 -0700 [thread overview]
Message-ID: <20190610020218.9228-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190610020218.9228-1-richard.henderson@linaro.org>
Cleanup in the boilerplate that each target must define.
Replace sh_env_get_cpu with env_archcpu. The combination
CPU(sh_env_get_cpu) should have used ENV_GET_CPU to begin;
use env_cpu now.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/cpu.h | 5 -----
linux-user/sh4/cpu_loop.c | 2 +-
target/sh4/helper.c | 26 ++++++++++++--------------
target/sh4/op_helper.c | 9 +++------
4 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 8b17e6d63e..089eea261c 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -207,11 +207,6 @@ struct SuperHCPU {
CPUSH4State env;
};
-static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env)
-{
- return container_of(env, SuperHCPU, env);
-}
-
#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
diff --git a/linux-user/sh4/cpu_loop.c b/linux-user/sh4/cpu_loop.c
index 59cbbeda7e..add8817d86 100644
--- a/linux-user/sh4/cpu_loop.c
+++ b/linux-user/sh4/cpu_loop.c
@@ -23,7 +23,7 @@
void cpu_loop(CPUSH4State *env)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int trapnr, ret;
target_siginfo_t info;
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index fda195e7cb..2afc1770d8 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -216,8 +216,6 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
static int itlb_replacement(CPUSH4State * env)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
-
if ((env->mmucr & 0xe0000000) == 0xe0000000) {
return 0;
}
@@ -230,7 +228,7 @@ static int itlb_replacement(CPUSH4State * env)
if ((env->mmucr & 0x2c000000) == 0x00000000) {
return 3;
}
- cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
+ cpu_abort(env_cpu(env), "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
@@ -286,7 +284,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
itlb = itlb_replacement(env);
ientry = &env->itlb[itlb];
if (ientry->v) {
- tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
+ tlb_flush_page(env_cpu(env), ientry->vpn << 10);
}
*ientry = env->utlb[utlb];
update_itlb_use(env, itlb);
@@ -448,14 +446,14 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void cpu_load_tlb(CPUSH4State * env)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
+ CPUState *cs = env_cpu(env);
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(cpu), address);
+ tlb_flush_page(cs, address);
}
/* Take values into cpu status from registers. */
@@ -478,7 +476,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->size = 1024 * 1024; /* 1M */
break;
default:
- cpu_abort(CPU(cpu), "Unhandled load_tlb");
+ cpu_abort(cs, "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
@@ -505,7 +503,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->v = 0;
}
- tlb_flush(CPU(sh_env_get_cpu(s)));
+ tlb_flush(env_cpu(s));
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
@@ -531,7 +529,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->asid = asid;
entry->vpn = vpn;
@@ -573,7 +571,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
@@ -626,7 +624,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) {
- CPUState *cs = CPU(sh_env_get_cpu(s));
+ CPUState *cs = env_cpu(s);
/* Multiple TLB Exception */
cs->exception_index = 0x140;
@@ -658,13 +656,13 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
}
if (needs_tlb_flush) {
- tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
+ tlb_flush_page(env_cpu(s), vpn << 10);
}
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
if (entry->v) {
- CPUState *cs = CPU(sh_env_get_cpu(s));
+ CPUState *cs = env_cpu(s);
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
@@ -719,7 +717,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
+ tlb_flush_page(env_cpu(s), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 932aa7a7c7..14c3db0f48 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -46,10 +46,7 @@ void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
- SuperHCPU *cpu = sh_env_get_cpu(env);
-
- /* XXXXX */
- cpu_abort(CPU(cpu), "Unhandled ldtlb");
+ cpu_abort(env_cpu(env), "Unhandled ldtlb");
#else
cpu_load_tlb(env);
#endif
@@ -58,7 +55,7 @@ void helper_ldtlb(CPUSH4State *env)
static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
uintptr_t retaddr)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit_restore(cs, retaddr);
@@ -91,7 +88,7 @@ void helper_debug(CPUSH4State *env)
void helper_sleep(CPUSH4State *env)
{
- CPUState *cs = CPU(sh_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->halted = 1;
env->in_sleep = 1;
--
2.17.1
next prev parent reply other threads:[~2019-06-10 2:28 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-10 2:01 [Qemu-devel] [PULL 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 01/39] tcg: Fold CPUTLBWindow into CPUTLBDesc Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 02/39] tcg: Split out target/arch/cpu-param.h Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 03/39] tcg: Create struct CPUTLB Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 04/39] cpu: Define CPUArchState with typedef Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 05/39] cpu: Define ArchCPU Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 06/39] cpu: Replace ENV_GET_CPU with env_cpu Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 07/39] cpu: Introduce env_archcpu Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 08/39] target/alpha: Use env_cpu, env_archcpu Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 09/39] target/arm: " Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 10/39] target/cris: Reindent mmu.c Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 11/39] target/cris: Reindent op_helper.c Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 12/39] target/cris: Use env_cpu, env_archcpu Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 13/39] target/hppa: " Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 14/39] target/i386: " Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 15/39] target/lm32: " Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 16/39] target/m68k: Use env_cpu Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 17/39] target/microblaze: Use env_cpu, env_archcpu Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 18/39] target/mips: " Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 19/39] target/moxie: " Richard Henderson
2019-06-10 2:01 ` [Qemu-devel] [PULL 20/39] target/nios2: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 21/39] target/openrisc: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 22/39] target/ppc: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 23/39] target/riscv: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 24/39] target/s390x: " Richard Henderson
2019-06-10 2:02 ` Richard Henderson [this message]
2019-06-10 2:02 ` [Qemu-devel] [PULL 26/39] target/sparc: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 27/39] target/tilegx: Use env_cpu Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 28/39] target/tricore: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 29/39] target/unicore32: Use env_cpu, env_archcpu Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 30/39] target/xtensa: " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 31/39] cpu: Move ENV_OFFSET to exec/gen-icount.h Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 32/39] cpu: Introduce cpu_set_cpustate_pointers Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 33/39] cpu: Introduce CPUNegativeOffsetState Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 34/39] cpu: Move icount_decr to CPUNegativeOffsetState Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 35/39] cpu: Move the softmmu tlb " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 36/39] cpu: Remove CPU_COMMON Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 37/39] tcg/aarch64: Use LDP to load tlb mask+table Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 38/39] tcg/arm: Use LDRD " Richard Henderson
2019-06-10 2:02 ` [Qemu-devel] [PULL 39/39] tcg/arm: Remove mostly unreachable tlb special case Richard Henderson
2019-06-10 2:51 ` [Qemu-devel] [PULL 00/39] tcg: Move the softmmu tlb to CPUNegativeOffsetState no-reply
2019-06-10 4:00 ` no-reply
2019-06-10 5:06 ` no-reply
2019-06-10 13:47 ` Peter Maydell
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