* [Qemu-devel] [PATCH 01/12] target/arm: Move vfp_expand_imm() to translate.[ch]
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:22 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 02/12] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm Peter Maydell
` (11 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
We want to use vfp_expand_imm() in the AArch32 VFP decode;
move it from the a64-only header/source file to the
AArch32 one (which is always compiled even for AArch64).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.h | 1 -
target/arm/translate.h | 7 +++++++
target/arm/translate-a64.c | 32 --------------------------------
target/arm/translate-vfp.inc.c | 33 +++++++++++++++++++++++++++++++++
4 files changed, 40 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index 9569bc5963d..9ab40872d85 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -39,7 +39,6 @@ void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
TCGv_ptr get_fpstatus_ptr(bool);
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
unsigned int imms, unsigned int immr);
-uint64_t vfp_expand_imm(int size, uint8_t imm8);
bool sve_access_check(DisasContext *s);
/* We should have at some point before trying to access an FP register
diff --git a/target/arm/translate.h b/target/arm/translate.h
index dc06dce7675..bc1617809da 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -237,6 +237,13 @@ static inline void gen_ss_advance(DisasContext *s)
}
}
+/*
+ * Given a VFP floating point constant encoded into an 8 bit immediate in an
+ * instruction, expand it to the actual constant value of the specified
+ * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
+ */
+uint64_t vfp_expand_imm(int size, uint8_t imm8);
+
/* Vector operations shared between ARM and AArch64. */
extern const GVecGen3 mla_op[4];
extern const GVecGen3 mls_op[4];
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ae739f65756..97f4164fbbc 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6380,38 +6380,6 @@ static void disas_fp_3src(DisasContext *s, uint32_t insn)
}
}
-/* The imm8 encodes the sign bit, enough bits to represent an exponent in
- * the range 01....1xx to 10....0xx, and the most significant 4 bits of
- * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
- */
-uint64_t vfp_expand_imm(int size, uint8_t imm8)
-{
- uint64_t imm;
-
- switch (size) {
- case MO_64:
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
- (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
- extract32(imm8, 0, 6);
- imm <<= 48;
- break;
- case MO_32:
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
- (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
- (extract32(imm8, 0, 6) << 3);
- imm <<= 16;
- break;
- case MO_16:
- imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
- (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
- (extract32(imm8, 0, 6) << 6);
- break;
- default:
- g_assert_not_reached();
- }
- return imm;
-}
-
/* Floating point immediate
* 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
* +---+---+---+-----------+------+---+------------+-------+------+------+
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 709fc65374d..a66084f6e36 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -30,6 +30,39 @@
#include "decode-vfp.inc.c"
#include "decode-vfp-uncond.inc.c"
+/*
+ * The imm8 encodes the sign bit, enough bits to represent an exponent in
+ * the range 01....1xx to 10....0xx, and the most significant 4 bits of
+ * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
+ */
+uint64_t vfp_expand_imm(int size, uint8_t imm8)
+{
+ uint64_t imm;
+
+ switch (size) {
+ case MO_64:
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
+ extract32(imm8, 0, 6);
+ imm <<= 48;
+ break;
+ case MO_32:
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
+ (extract32(imm8, 0, 6) << 3);
+ imm <<= 16;
+ break;
+ case MO_16:
+ imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
+ (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
+ (extract32(imm8, 0, 6) << 6);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return imm;
+}
+
/*
* Return the offset of a 16-bit half of the specified VFP single-precision
* register. If top is true, returns the top 16 bits; otherwise the bottom
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH 01/12] target/arm: Move vfp_expand_imm() to translate.[ch]
2019-06-13 16:39 ` [Qemu-devel] [PATCH 01/12] target/arm: Move vfp_expand_imm() to translate.[ch] Peter Maydell
@ 2019-06-13 21:22 ` Richard Henderson
0 siblings, 0 replies; 26+ messages in thread
From: Richard Henderson @ 2019-06-13 21:22 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
On 6/13/19 9:39 AM, Peter Maydell wrote:
> We want to use vfp_expand_imm() in the AArch32 VFP decode;
> move it from the a64-only header/source file to the
> AArch32 one (which is always compiled even for AArch64).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/translate-a64.h | 1 -
> target/arm/translate.h | 7 +++++++
> target/arm/translate-a64.c | 32 --------------------------------
> target/arm/translate-vfp.inc.c | 33 +++++++++++++++++++++++++++++++++
> 4 files changed, 40 insertions(+), 33 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH 02/12] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
2019-06-13 16:39 ` [Qemu-devel] [PATCH 01/12] target/arm: Move vfp_expand_imm() to translate.[ch] Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:23 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 03/12] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F Peter Maydell
` (10 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
The AArch32 VMOV (immediate) instruction uses the same VFP encoded
immediate format we already handle in vfp_expand_imm(). Use that
function rather than hand-decoding it.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-vfp.inc.c | 28 ++++------------------------
target/arm/vfp.decode | 10 ++++++----
2 files changed, 10 insertions(+), 28 deletions(-)
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index a66084f6e36..8b732761f26 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1842,7 +1842,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i32 fd;
- uint32_t n, i, vd;
+ uint32_t vd;
vd = a->vd;
@@ -1869,17 +1869,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a)
}
}
- n = (a->imm4h << 28) & 0x80000000;
- i = ((a->imm4h << 4) & 0x70) | a->imm4l;
- if (i & 0x40) {
- i |= 0x780;
- } else {
- i |= 0x800;
- }
- n |= i << 19;
-
- fd = tcg_temp_new_i32();
- tcg_gen_movi_i32(fd, n);
+ fd = tcg_const_i32(vfp_expand_imm(MO_32, a->imm));
for (;;) {
neon_store_reg32(fd, vd);
@@ -1902,7 +1892,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
uint32_t delta_d = 0;
int veclen = s->vec_len;
TCGv_i64 fd;
- uint32_t n, i, vd;
+ uint32_t vd;
vd = a->vd;
@@ -1934,17 +1924,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
}
}
- n = (a->imm4h << 28) & 0x80000000;
- i = ((a->imm4h << 4) & 0x70) | a->imm4l;
- if (i & 0x40) {
- i |= 0x3f80;
- } else {
- i |= 0x4000;
- }
- n |= i << 16;
-
- fd = tcg_temp_new_i64();
- tcg_gen_movi_i64(fd, ((uint64_t)n) << 32);
+ fd = tcg_const_i64(vfp_expand_imm(MO_64, a->imm));
for (;;) {
neon_store_reg64(fd, vd);
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index ea24365bb4c..a67b3f29ee5 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -44,6 +44,8 @@
%vmov_idx_b 21:1 5:2
%vmov_idx_h 21:1 6:1
+%vmov_imm 16:4 0:4
+
# VMOV scalar to general-purpose register; note that this does
# include some Neon cases.
VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
@@ -152,10 +154,10 @@ VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \
VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
-VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \
- vd=%vd_sp
-VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \
- vd=%vd_dp
+VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
+ vd=%vd_sp imm=%vmov_imm
+VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
+ vd=%vd_dp imm=%vmov_imm
VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \
vd=%vd_sp vm=%vm_sp
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 03/12] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
2019-06-13 16:39 ` [Qemu-devel] [PATCH 01/12] target/arm: Move vfp_expand_imm() to translate.[ch] Peter Maydell
2019-06-13 16:39 ` [Qemu-devel] [PATCH 02/12] target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:25 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 04/12] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F Peter Maydell
` (9 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Where Neon instructions are floating point operations, we
mostly use the old VFP utility functions like gen_vfp_abs()
which work on the TCG globals cpu_F0s and cpu_F1s. The
Neon for-each-element loop conditionally loads the inputs
into either a plain old TCG temporary for most operations
or into cpu_F0s for float operations, and similarly stores
back either cpu_F0s or the temporary.
Switch NEON_2RM_VABS_F away from using cpu_F0s, and
update neon_2rm_is_float_op() accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c274c8b4602..a10fded1f39 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1374,14 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
return statusptr;
}
-static inline void gen_vfp_abs(int dp)
-{
- if (dp)
- gen_helper_vfp_absd(cpu_F0d, cpu_F0d);
- else
- gen_helper_vfp_abss(cpu_F0s, cpu_F0s);
-}
-
static inline void gen_vfp_neg(int dp)
{
if (dp)
@@ -4191,8 +4183,13 @@ static const uint8_t neon_3r_sizes[] = {
static int neon_2rm_is_float_op(int op)
{
- /* Return true if this neon 2reg-misc op is float-to-float */
- return (op == NEON_2RM_VABS_F || op == NEON_2RM_VNEG_F ||
+ /*
+ * Return true if this neon 2reg-misc op is float-to-float.
+ * This is not a property of the operation but of our code --
+ * what we are asking here is "does the code for this case in
+ * the Neon for-each-pass loop use cpu_F0s?".
+ */
+ return (op == NEON_2RM_VNEG_F ||
(op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
op == NEON_2RM_VRINTM ||
(op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
@@ -6761,7 +6758,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break;
}
case NEON_2RM_VABS_F:
- gen_vfp_abs(0);
+ gen_helper_vfp_abss(tmp, tmp);
break;
case NEON_2RM_VNEG_F:
gen_vfp_neg(0);
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH 03/12] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F
2019-06-13 16:39 ` [Qemu-devel] [PATCH 03/12] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F Peter Maydell
@ 2019-06-13 21:25 ` Richard Henderson
0 siblings, 0 replies; 26+ messages in thread
From: Richard Henderson @ 2019-06-13 21:25 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
On 6/13/19 9:39 AM, Peter Maydell wrote:
> Where Neon instructions are floating point operations, we
> mostly use the old VFP utility functions like gen_vfp_abs()
> which work on the TCG globals cpu_F0s and cpu_F1s. The
> Neon for-each-element loop conditionally loads the inputs
> into either a plain old TCG temporary for most operations
> or into cpu_F0s for float operations, and similarly stores
> back either cpu_F0s or the temporary.
>
> Switch NEON_2RM_VABS_F away from using cpu_F0s, and
> update neon_2rm_is_float_op() accordingly.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/translate.c | 19 ++++++++-----------
> 1 file changed, 8 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Qemu-devel] [PATCH 04/12] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (2 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 03/12] target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:25 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 05/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* Peter Maydell
` (8 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Switch NEON_2RM_VABS_F away from using cpu_F0s.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a10fded1f39..a006ab498e7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1374,14 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
return statusptr;
}
-static inline void gen_vfp_neg(int dp)
-{
- if (dp)
- gen_helper_vfp_negd(cpu_F0d, cpu_F0d);
- else
- gen_helper_vfp_negs(cpu_F0s, cpu_F0s);
-}
-
#define VFP_GEN_ITOF(name) \
static inline void gen_vfp_##name(int dp, int neon) \
{ \
@@ -4189,8 +4181,7 @@ static int neon_2rm_is_float_op(int op)
* what we are asking here is "does the code for this case in
* the Neon for-each-pass loop use cpu_F0s?".
*/
- return (op == NEON_2RM_VNEG_F ||
- (op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
+ return ((op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
op == NEON_2RM_VRINTM ||
(op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
op >= NEON_2RM_VRECPE_F);
@@ -6761,7 +6752,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
gen_helper_vfp_abss(tmp, tmp);
break;
case NEON_2RM_VNEG_F:
- gen_vfp_neg(0);
+ gen_helper_vfp_negs(tmp, tmp);
break;
case NEON_2RM_VSWP:
tmp2 = neon_load_reg(rd, pass);
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 05/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (3 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 04/12] target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:26 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 06/12] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] Peter Maydell
` (7 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Switch NEON_2RM_VRINT* away from using cpu_F0s.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index a006ab498e7..243dbee8357 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4181,9 +4181,7 @@ static int neon_2rm_is_float_op(int op)
* what we are asking here is "does the code for this case in
* the Neon for-each-pass loop use cpu_F0s?".
*/
- return ((op >= NEON_2RM_VRINTN && op <= NEON_2RM_VRINTZ) ||
- op == NEON_2RM_VRINTM ||
- (op >= NEON_2RM_VRINTP && op <= NEON_2RM_VCVTMS) ||
+ return ((op >= NEON_2RM_VCVTAU && op <= NEON_2RM_VCVTMS) ||
op >= NEON_2RM_VRECPE_F);
}
@@ -6786,7 +6784,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
cpu_env);
- gen_helper_rints(cpu_F0s, cpu_F0s, fpstatus);
+ gen_helper_rints(tmp, tmp, fpstatus);
gen_helper_set_neon_rmode(tcg_rmode, tcg_rmode,
cpu_env);
tcg_temp_free_ptr(fpstatus);
@@ -6796,7 +6794,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VRINTX:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- gen_helper_rints_exact(cpu_F0s, cpu_F0s, fpstatus);
+ gen_helper_rints_exact(tmp, tmp, fpstatus);
tcg_temp_free_ptr(fpstatus);
break;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 06/12] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (4 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 05/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRINT* Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:27 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 07/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F Peter Maydell
` (6 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Stop using cpu_F0s for the NEON_2RM_VCVT[ANPM][US] ops.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 243dbee8357..124045a9ef6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4181,8 +4181,7 @@ static int neon_2rm_is_float_op(int op)
* what we are asking here is "does the code for this case in
* the Neon for-each-pass loop use cpu_F0s?".
*/
- return ((op >= NEON_2RM_VCVTAU && op <= NEON_2RM_VCVTMS) ||
- op >= NEON_2RM_VRECPE_F);
+ return op >= NEON_2RM_VRECPE_F;
}
static bool neon_2rm_is_v8_op(int op)
@@ -6818,10 +6817,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
cpu_env);
if (is_signed) {
- gen_helper_vfp_tosls(cpu_F0s, cpu_F0s,
+ gen_helper_vfp_tosls(tmp, tmp,
tcg_shift, fpst);
} else {
- gen_helper_vfp_touls(cpu_F0s, cpu_F0s,
+ gen_helper_vfp_touls(tmp, tmp,
tcg_shift, fpst);
}
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 07/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (5 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 06/12] target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US] Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:28 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 08/12] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT Peter Maydell
` (5 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 124045a9ef6..75ed7cc7cb0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4181,7 +4181,7 @@ static int neon_2rm_is_float_op(int op)
* what we are asking here is "does the code for this case in
* the Neon for-each-pass loop use cpu_F0s?".
*/
- return op >= NEON_2RM_VRECPE_F;
+ return op >= NEON_2RM_VCVT_FS;
}
static bool neon_2rm_is_v8_op(int op)
@@ -6848,14 +6848,14 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VRECPE_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- gen_helper_recpe_f32(cpu_F0s, cpu_F0s, fpstatus);
+ gen_helper_recpe_f32(tmp, tmp, fpstatus);
tcg_temp_free_ptr(fpstatus);
break;
}
case NEON_2RM_VRSQRTE_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
- gen_helper_rsqrte_f32(cpu_F0s, cpu_F0s, fpstatus);
+ gen_helper_rsqrte_f32(tmp, tmp, fpstatus);
tcg_temp_free_ptr(fpstatus);
break;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 08/12] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (6 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 07/12] target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:29 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 09/12] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops Peter Maydell
` (4 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Stop using cpu_F0s for the Neon f32/s32 VCVT operations.
Since this is the last user of cpu_F0s in the Neon 2rm-op
loop, we can remove the handling code for it too.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 82 ++++++++++++------------------------------
1 file changed, 22 insertions(+), 60 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 75ed7cc7cb0..0fb94b777bf 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1374,38 +1374,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
return statusptr;
}
-#define VFP_GEN_ITOF(name) \
-static inline void gen_vfp_##name(int dp, int neon) \
-{ \
- TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
- if (dp) { \
- gen_helper_vfp_##name##d(cpu_F0d, cpu_F0s, statusptr); \
- } else { \
- gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
- } \
- tcg_temp_free_ptr(statusptr); \
-}
-
-VFP_GEN_ITOF(uito)
-VFP_GEN_ITOF(sito)
-#undef VFP_GEN_ITOF
-
-#define VFP_GEN_FTOI(name) \
-static inline void gen_vfp_##name(int dp, int neon) \
-{ \
- TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
- if (dp) { \
- gen_helper_vfp_##name##d(cpu_F0s, cpu_F0d, statusptr); \
- } else { \
- gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, statusptr); \
- } \
- tcg_temp_free_ptr(statusptr); \
-}
-
-VFP_GEN_FTOI(touiz)
-VFP_GEN_FTOI(tosiz)
-#undef VFP_GEN_FTOI
-
#define VFP_GEN_FIX(name, round) \
static inline void gen_vfp_##name(int dp, int shift, int neon) \
{ \
@@ -4173,17 +4141,6 @@ static const uint8_t neon_3r_sizes[] = {
#define NEON_2RM_VCVT_SF 62
#define NEON_2RM_VCVT_UF 63
-static int neon_2rm_is_float_op(int op)
-{
- /*
- * Return true if this neon 2reg-misc op is float-to-float.
- * This is not a property of the operation but of our code --
- * what we are asking here is "does the code for this case in
- * the Neon for-each-pass loop use cpu_F0s?".
- */
- return op >= NEON_2RM_VCVT_FS;
-}
-
static bool neon_2rm_is_v8_op(int op)
{
/* Return true if this neon 2reg-misc op is ARMv8 and up */
@@ -6599,13 +6556,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
default:
elementwise:
for (pass = 0; pass < (q ? 4 : 2); pass++) {
- if (neon_2rm_is_float_op(op)) {
- tcg_gen_ld_f32(cpu_F0s, cpu_env,
- neon_reg_offset(rm, pass));
- tmp = NULL;
- } else {
- tmp = neon_load_reg(rm, pass);
- }
+ tmp = neon_load_reg(rm, pass);
switch (op) {
case NEON_2RM_VREV32:
switch (size) {
@@ -6860,29 +6811,40 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break;
}
case NEON_2RM_VCVT_FS: /* VCVT.F32.S32 */
- gen_vfp_sito(0, 1);
+ {
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ gen_helper_vfp_sitos(tmp, tmp, fpstatus);
+ tcg_temp_free_ptr(fpstatus);
break;
+ }
case NEON_2RM_VCVT_FU: /* VCVT.F32.U32 */
- gen_vfp_uito(0, 1);
+ {
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ gen_helper_vfp_uitos(tmp, tmp, fpstatus);
+ tcg_temp_free_ptr(fpstatus);
break;
+ }
case NEON_2RM_VCVT_SF: /* VCVT.S32.F32 */
- gen_vfp_tosiz(0, 1);
+ {
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ gen_helper_vfp_tosizs(tmp, tmp, fpstatus);
+ tcg_temp_free_ptr(fpstatus);
break;
+ }
case NEON_2RM_VCVT_UF: /* VCVT.U32.F32 */
- gen_vfp_touiz(0, 1);
+ {
+ TCGv_ptr fpstatus = get_fpstatus_ptr(1);
+ gen_helper_vfp_touizs(tmp, tmp, fpstatus);
+ tcg_temp_free_ptr(fpstatus);
break;
+ }
default:
/* Reserved op values were caught by the
* neon_2rm_sizes[] check earlier.
*/
abort();
}
- if (neon_2rm_is_float_op(op)) {
- tcg_gen_st_f32(cpu_F0s, cpu_env,
- neon_reg_offset(rd, pass));
- } else {
- neon_store_reg(rd, pass, tmp);
- }
+ neon_store_reg(rd, pass, tmp);
}
break;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 09/12] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (7 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 08/12] target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:31 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 10/12] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 Peter Maydell
` (3 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Stop using cpu_F0s in the Neon VCVT fixed-point operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 62 +++++++++++++++++++-----------------------
1 file changed, 28 insertions(+), 34 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0fb94b777bf..d8b46130d42 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -80,6 +80,8 @@ static const char * const regnames[] =
/* Function prototypes for gen_ functions calling Neon helpers. */
typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
TCGv_i32, TCGv_i32);
+/* Function prototypes for gen_ functions for fix point conversions */
+typedef void VFPGenFixPointFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
/* initialize TCG globals. */
void arm_translate_init(void)
@@ -1374,27 +1376,6 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
return statusptr;
}
-#define VFP_GEN_FIX(name, round) \
-static inline void gen_vfp_##name(int dp, int shift, int neon) \
-{ \
- TCGv_i32 tmp_shift = tcg_const_i32(shift); \
- TCGv_ptr statusptr = get_fpstatus_ptr(neon); \
- if (dp) { \
- gen_helper_vfp_##name##d##round(cpu_F0d, cpu_F0d, tmp_shift, \
- statusptr); \
- } else { \
- gen_helper_vfp_##name##s##round(cpu_F0s, cpu_F0s, tmp_shift, \
- statusptr); \
- } \
- tcg_temp_free_i32(tmp_shift); \
- tcg_temp_free_ptr(statusptr); \
-}
-VFP_GEN_FIX(tosl, _round_to_zero)
-VFP_GEN_FIX(toul, _round_to_zero)
-VFP_GEN_FIX(slto, )
-VFP_GEN_FIX(ulto, )
-#undef VFP_GEN_FIX
-
static inline long vfp_reg_offset(bool dp, unsigned reg)
{
if (dp) {
@@ -5721,28 +5702,41 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
} else if (op >= 14) {
/* VCVT fixed-point. */
+ TCGv_ptr fpst;
+ TCGv_i32 shiftv;
+ VFPGenFixPointFn *fn;
+
if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
return 1;
}
+
+ if (!(op & 1)) {
+ if (u) {
+ fn = gen_helper_vfp_ultos;
+ } else {
+ fn = gen_helper_vfp_sltos;
+ }
+ } else {
+ if (u) {
+ fn = gen_helper_vfp_touls_round_to_zero;
+ } else {
+ fn = gen_helper_vfp_tosls_round_to_zero;
+ }
+ }
+
/* We have already masked out the must-be-1 top bit of imm6,
* hence this 32-shift where the ARM ARM has 64-imm6.
*/
shift = 32 - shift;
+ fpst = get_fpstatus_ptr(1);
+ shiftv = tcg_const_i32(shift);
for (pass = 0; pass < (q ? 4 : 2); pass++) {
- tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass));
- if (!(op & 1)) {
- if (u)
- gen_vfp_ulto(0, shift, 1);
- else
- gen_vfp_slto(0, shift, 1);
- } else {
- if (u)
- gen_vfp_toul(0, shift, 1);
- else
- gen_vfp_tosl(0, shift, 1);
- }
- tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, pass));
+ TCGv_i32 tmpf = neon_load_reg(rm, pass);
+ fn(tmpf, tmpf, shiftv, fpst);
+ neon_store_reg(rd, pass, tmpf);
}
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(shiftv);
} else {
return 1;
}
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 10/12] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (8 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 09/12] target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:33 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 11/12] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 Peter Maydell
` (2 subsequent siblings)
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Remove some old constructs from NEON_2RM_VCVT_F16_F32 code:
* don't use cpu_F0s
* don't use tcg_gen_ld_f32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d8b46130d42..2ba620ac1e1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1542,7 +1542,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
return ret;
}
-#define tcg_gen_ld_f32 tcg_gen_ld_i32
#define tcg_gen_st_f32 tcg_gen_st_i32
#define ARM_CP_RW_BIT (1 << 20)
@@ -6425,25 +6424,23 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
q || (rm & 1)) {
return 1;
}
- tmp = tcg_temp_new_i32();
- tmp2 = tcg_temp_new_i32();
fpst = get_fpstatus_ptr(true);
ahp = get_ahp_flag();
- tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 0));
- gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp);
- tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 1));
- gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp);
+ tmp = neon_load_reg(rm, 0);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
+ tmp2 = neon_load_reg(rm, 1);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp);
tcg_gen_shli_i32(tmp2, tmp2, 16);
tcg_gen_or_i32(tmp2, tmp2, tmp);
- tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 2));
- gen_helper_vfp_fcvt_f32_to_f16(tmp, cpu_F0s, fpst, ahp);
- tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, 3));
+ tcg_temp_free_i32(tmp);
+ tmp = neon_load_reg(rm, 2);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp);
+ tmp3 = neon_load_reg(rm, 3);
neon_store_reg(rd, 0, tmp2);
- tmp2 = tcg_temp_new_i32();
- gen_helper_vfp_fcvt_f32_to_f16(tmp2, cpu_F0s, fpst, ahp);
- tcg_gen_shli_i32(tmp2, tmp2, 16);
- tcg_gen_or_i32(tmp2, tmp2, tmp);
- neon_store_reg(rd, 1, tmp2);
+ gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp);
+ tcg_gen_shli_i32(tmp3, tmp3, 16);
+ tcg_gen_or_i32(tmp3, tmp3, tmp);
+ neon_store_reg(rd, 1, tmp3);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(ahp);
tcg_temp_free_ptr(fpst);
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 11/12] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (9 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 10/12] target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32 Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:34 ` Richard Henderson
2019-06-13 16:39 ` [Qemu-devel] [PATCH 12/12] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d Peter Maydell
2019-06-14 5:27 ` [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Philippe Mathieu-Daudé
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Remove some old constructns from NEON_2RM_VCVT_F16_F32 code:
* don't use CPU_F0s
* don't use tcg_gen_st_f32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2ba620ac1e1..8f124a953b6 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1542,8 +1542,6 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
return ret;
}
-#define tcg_gen_st_f32 tcg_gen_st_i32
-
#define ARM_CP_RW_BIT (1 << 20)
/* Include the VFP decoder */
@@ -6460,20 +6458,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp = neon_load_reg(rm, 0);
tmp2 = neon_load_reg(rm, 1);
tcg_gen_ext16u_i32(tmp3, tmp);
- gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp);
- tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 0));
- tcg_gen_shri_i32(tmp3, tmp, 16);
- gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp);
- tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 1));
- tcg_temp_free_i32(tmp);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
+ neon_store_reg(rd, 0, tmp3);
+ tcg_gen_shri_i32(tmp, tmp, 16);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp);
+ neon_store_reg(rd, 1, tmp);
+ tmp3 = tcg_temp_new_i32();
tcg_gen_ext16u_i32(tmp3, tmp2);
- gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp);
- tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 2));
- tcg_gen_shri_i32(tmp3, tmp2, 16);
- gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s, tmp3, fpst, ahp);
- tcg_gen_st_f32(cpu_F0s, cpu_env, neon_reg_offset(rd, 3));
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i32(tmp3);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp);
+ neon_store_reg(rd, 2, tmp3);
+ tcg_gen_shri_i32(tmp2, tmp2, 16);
+ gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp);
+ neon_store_reg(rd, 3, tmp2);
tcg_temp_free_i32(ahp);
tcg_temp_free_ptr(fpst);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [Qemu-devel] [PATCH 12/12] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (10 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 11/12] target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16 Peter Maydell
@ 2019-06-13 16:39 ` Peter Maydell
2019-06-13 21:35 ` Richard Henderson
2019-06-14 5:27 ` [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Philippe Mathieu-Daudé
12 siblings, 1 reply; 26+ messages in thread
From: Peter Maydell @ 2019-06-13 16:39 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
Remove the now unused TCG globals cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d.
cpu_M0 is still used by the iwmmxt code, and cpu_V0 and
cpu_V1 are used by both iwmmxt and Neon.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8f124a953b6..4750b9fa1bb 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -67,10 +67,6 @@ TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF;
TCGv_i64 cpu_exclusive_addr;
TCGv_i64 cpu_exclusive_val;
-/* FIXME: These should be removed. */
-static TCGv_i32 cpu_F0s, cpu_F1s;
-static TCGv_i64 cpu_F0d, cpu_F1d;
-
#include "exec/gen-icount.h"
static const char * const regnames[] =
@@ -11911,12 +11907,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->base.max_insns = MIN(dc->base.max_insns, bound);
}
- cpu_F0s = tcg_temp_new_i32();
- cpu_F1s = tcg_temp_new_i32();
- cpu_F0d = tcg_temp_new_i64();
- cpu_F1d = tcg_temp_new_i64();
- cpu_V0 = cpu_F0d;
- cpu_V1 = cpu_F1d;
+ cpu_V0 = tcg_temp_new_i64();
+ cpu_V1 = tcg_temp_new_i64();
/* FIXME: cpu_M0 can probably be the same as cpu_V0. */
cpu_M0 = tcg_temp_new_i64();
}
--
2.20.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [Qemu-devel] [PATCH 12/12] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d
2019-06-13 16:39 ` [Qemu-devel] [PATCH 12/12] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d Peter Maydell
@ 2019-06-13 21:35 ` Richard Henderson
0 siblings, 0 replies; 26+ messages in thread
From: Richard Henderson @ 2019-06-13 21:35 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel
On 6/13/19 9:39 AM, Peter Maydell wrote:
> Remove the now unused TCG globals cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d.
>
> cpu_M0 is still used by the iwmmxt code, and cpu_V0 and
> cpu_V1 are used by both iwmmxt and Neon.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/translate.c | 12 ++----------
> 1 file changed, 2 insertions(+), 10 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups
2019-06-13 16:39 [Qemu-devel] [PATCH 00/12] target/arm: VFP decodetree conversion followups Peter Maydell
` (11 preceding siblings ...)
2019-06-13 16:39 ` [Qemu-devel] [PATCH 12/12] target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d Peter Maydell
@ 2019-06-14 5:27 ` Philippe Mathieu-Daudé
12 siblings, 0 replies; 26+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-06-14 5:27 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Richard Henderson
On 6/13/19 6:39 PM, Peter Maydell wrote:
> This patchset does a couple of the cleanup/leftover things noted
> in the coverletter of the vfp decodetree conversion or discussed
> in code review:
> * use vfp_expand_imm() for doing the VFP const-immediate
> decode, rather than hand-coding it
> * get rid of the final uses of cpu_F[01][sd]
>
> cpu_V0, cpu_V1 and cpu_M0 will have to wait until somebody
> cares to tackle the Neon decode logic and the iwmmxt decode...
>
> thanks
> -- PMM
>
> Peter Maydell (12):
> target/arm: Move vfp_expand_imm() to translate.[ch]
> target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_imm
> target/arm: Stop using cpu_F0s for NEON_2RM_VABS_F
> target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_F
> target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*
> target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]
> target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and
> NEON_2RM_VRSQRTE_F
> target/arm: Stop using cpu_F0s for Neon f32/s32 VCVT
> target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops
> target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32
> target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16
> target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d
>
> target/arm/translate-a64.h | 1 -
> target/arm/translate.h | 7 +
> target/arm/translate-a64.c | 32 -----
> target/arm/translate-vfp.inc.c | 61 +++++----
> target/arm/translate.c | 240 ++++++++++++---------------------
> target/arm/vfp.decode | 10 +-
> 6 files changed, 133 insertions(+), 218 deletions(-)
>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 26+ messages in thread