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[60.43.49.30]) by smtp.gmail.com with ESMTPSA id o20sm7996858pgj.70.2019.06.16.07.23.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 16 Jun 2019 07:23:06 -0700 (PDT) Date: Sun, 16 Jun 2019 23:23:03 +0900 From: Lucien Murray-Pitts To: qemu-devel@nongnu.org, Laurent Vivier , Lucien Murray-Pitts Message-ID: <20190616142303.GA71209@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.11.4 (2019-03-13) X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 5/6] MOVEC insn. doesnt generate exception if wrong CR is accessed X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Added "CPU class" m68k_feature to each CPU init func so MOVEC can detect wrong CR (Control Register) access. Added CPU class detection for each CR type in the m68k_move_to/from helpers, so that it throws and exception if an unsupported register is requested for that CPU class. Reclassified MOVEC insn. as only supported in 68010. Signed-off-by: Lucien Murray-Pitts --- target/m68k/cpu.c | 3 + target/m68k/cpu.h | 4 + target/m68k/helper.c | 192 ++++++++++++++++++++++++++++++---------- target/m68k/translate.c | 2 +- 4 files changed, 155 insertions(+), 46 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f3246d6e72..50260de97d 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -134,6 +134,7 @@ static void m68010_cpu_initfn(Object *obj) CPUM68KState *env = &cpu->env; m68000_cpu_initfn(obj); + m68k_set_feature(env, M68K_FEATURE_M68010); m68k_set_feature(env, M68K_FEATURE_RTD); m68k_set_feature(env, M68K_FEATURE_BKPT); } @@ -151,6 +152,7 @@ static void m68020_cpu_initfn(Object *obj) CPUM68KState *env = &cpu->env; m68010_cpu_initfn(obj); + m68k_set_feature(env, M68K_FEATURE_M68020); m68k_set_feature(env, M68K_FEATURE_QUAD_MULDIV); m68k_set_feature(env, M68K_FEATURE_BRAL); m68k_set_feature(env, M68K_FEATURE_BCCL); @@ -177,6 +179,7 @@ static void m68030_cpu_initfn(Object *obj) CPUM68KState *env = &cpu->env; m68020_cpu_initfn(obj); + m68k_set_feature(env, M68K_FEATURE_M68030); } diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 2386419c42..86ba19f779 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -488,7 +488,11 @@ void do_m68k_semihosting(CPUM68KState *env, int nr); enum m68k_features { M68K_FEATURE_M68000, /* Base m68k instruction set */ + M68K_FEATURE_M68010, /* Additional insn. specific to MC68010 */ + M68K_FEATURE_M68020, /* Additional insn. specific to MC68020 */ + M68K_FEATURE_M68030, /* Additional insn. specific to MC68030 */ M68K_FEATURE_M68040, /* Additional insn. specific to MC68040 */ + M68K_FEATURE_M68060, /* Additional insn. specific to MC68060 */ M68K_FEATURE_CF_ISA_A, /* Base Coldfire set Rev A. */ M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */ M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */ diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 47b352c9c9..119fc3af2b 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -192,6 +192,16 @@ void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) } } + + +static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +{ + CPUState *cs = CPU(m68k_env_get_cpu(env)); + + cs->exception_index = tt; + cpu_loop_exit_restore(cs, raddr); +} + void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) { M68kCPU *cpu = m68k_env_get_cpu(env); @@ -211,52 +221,96 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) return; /* MC680[2346]0 */ case M68K_CR_CACR: - env->cacr = val; - m68k_switch_sp(env); - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->cacr = val; + m68k_switch_sp(env); + return; + } + break; /* MC680[46]0 */ case M68K_CR_TC: - env->mmu.tcr = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.tcr = val; + return; + } + break; /* MC680[4]0 */ case M68K_CR_MMUSR: - env->mmu.mmusr = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.mmusr = val; + return; + } + break; /* MC680[46]0 */ case M68K_CR_SRP: - env->mmu.srp = val; - return; - case M68K_CR_URP: - env->mmu.urp = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.srp = val; + return; + } + break; /* MC680[46]0 */ + case M68K_CR_URP: + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + env->mmu.urp = val; + return; + } + break; + /* MC680[12346]0 */ case M68K_CR_USP: env->sp[M68K_USP] = val; return; /* MC680[234]0 */ case M68K_CR_MSP: - env->sp[M68K_SSP] = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + env->sp[M68K_SSP] = val; + return; + } + break; /* MC680[234]0 */ case M68K_CR_ISP: - env->sp[M68K_ISP] = val; - return; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + env->sp[M68K_ISP] = val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_ITT0: - env->mmu.ttr[M68K_ITTR0] = val; - return; + case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_ITTR0] = val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_ITT1: - env->mmu.ttr[M68K_ITTR1] = val; - return; + case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_ITTR1] = val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_DTT0: - env->mmu.ttr[M68K_DTTR0] = val; - return; + case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_DTTR0] = val; + return; + } + break; /* MC68040/MC68LC040 */ - case M68K_CR_DTT1: - env->mmu.ttr[M68K_DTTR1] = val; - return; + case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */ + if (m68k_feature(env, M68K_FEATURE_M68040)) { + env->mmu.ttr[M68K_DTTR1] = val; + return; + } + break; /* Unimplemented Registers */ case M68K_CR_CAAR: case M68K_CR_PCR: @@ -266,8 +320,10 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val) reg, val); return; } - cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n", - reg, val); + + /* Invalid control registers will generate an exception. */ + raise_exception_ra(env, EXCP_ILLEGAL, 0); + return; } uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) @@ -286,40 +342,83 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) return env->vbr; /* MC680[2346]0 */ case M68K_CR_CACR: - return env->cacr; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->cacr; + } + break; /* MC680[46]0 */ case M68K_CR_TC: - return env->mmu.tcr; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.tcr; + } + break; /* MC680[4]0 */ case M68K_CR_MMUSR: - return env->mmu.mmusr; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.mmusr; + } + break; /* MC680[46]0 */ case M68K_CR_SRP: - return env->mmu.srp; + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.srp; + } + break; + /* MC68040/MC68LC040 */ + case M68K_CR_URP: + if (m68k_feature(env, M68K_FEATURE_M68040) + || m68k_feature(env, M68K_FEATURE_M68060)) { + return env->mmu.urp; + } + break; /* MC680[46]0 */ case M68K_CR_USP: return env->sp[M68K_USP]; /* MC680[234]0 */ case M68K_CR_MSP: - return env->sp[M68K_SSP]; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + return env->sp[M68K_SSP]; + } + break; /* MC680[234]0 */ case M68K_CR_ISP: - return env->sp[M68K_ISP]; - /* MC68040/MC68LC040 */ - case M68K_CR_URP: - return env->mmu.urp; + if (m68k_feature(env, M68K_FEATURE_M68020) + || m68k_feature(env, M68K_FEATURE_M68030) + || m68k_feature(env, M68K_FEATURE_M68040)) { + return env->sp[M68K_ISP]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_ITT0: /* MC68EC040 only: M68K_CR_IACR0 */ - return env->mmu.ttr[M68K_ITTR0]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_ITTR0]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_ITT1: /* MC68EC040 only: M68K_CR_IACR1 */ - return env->mmu.ttr[M68K_ITTR1]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_ITTR1]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_DTT0: /* MC68EC040 only: M68K_CR_DACR0 */ - return env->mmu.ttr[M68K_DTTR0]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_DTTR0]; + } + break; /* MC68040/MC68LC040 */ case M68K_CR_DTT1: /* MC68EC040 only: M68K_CR_DACR1 */ - return env->mmu.ttr[M68K_DTTR1]; + if (m68k_feature(env, M68K_FEATURE_M68040)) { + return env->mmu.ttr[M68K_DTTR1]; + } + break; /* Unimplemented Registers */ case M68K_CR_CAAR: case M68K_CR_PCR: @@ -327,8 +426,11 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg) cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", reg); } - cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n", - reg); + + /* Invalid control registers will generate an exception. */ + raise_exception_ra(env, EXCP_ILLEGAL, 0); + + return 0; } void HELPER(set_macsr)(CPUM68KState *env, uint32_t val) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 9b0ca4c14c..cbca02a7b5 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5990,7 +5990,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(stop, 4e72, ffff); BASE(rte, 4e73, ffff); INSN(cf_movec, 4e7b, ffff, CF_ISA_A); - INSN(m68k_movec, 4e7a, fffe, M68000); + INSN(m68k_movec, 4e7a, fffe, M68010); #endif BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); -- 2.21.0