From: "Michael S. Tsirkin" <mst@redhat.com>
To: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally
Date: Mon, 17 Jun 2019 21:26:31 -0400 [thread overview]
Message-ID: <20190617212626-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20190416013902.4941-4-andrew.smirnov@gmail.com>
On Mon, Apr 15, 2019 at 06:39:00PM -0700, Andrey Smirnov wrote:
> Expression to calculate update_msi_mapping in code handling writes to
> DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
> be:
>
> !!root->msi.intr[0].enable ^ !!val;
>
> so that MSI mapping is updated when enabled transitions from either
> "none" -> "any" or "any" -> "none". Since that register shouldn't be
> written to very often, change the code to update MSI mapping
> unconditionally instead of trying to fix the update_msi_mapping logic.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Cc: qemu-devel@nongnu.org
> Cc: qemu-arm@nongnu.org
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/pci-host/designware.c | 10 ++--------
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
> index 29ea313798..6affe823c0 100644
> --- a/hw/pci-host/designware.c
> +++ b/hw/pci-host/designware.c
> @@ -296,16 +296,10 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address,
> root->msi.base |= (uint64_t)val << 32;
> break;
>
> - case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: {
> - const bool update_msi_mapping = !root->msi.intr[0].enable ^ !!val;
> -
> + case DESIGNWARE_PCIE_MSI_INTR0_ENABLE:
> root->msi.intr[0].enable = val;
> -
> - if (update_msi_mapping) {
> - designware_pcie_root_update_msi_mapping(root);
> - }
> + designware_pcie_root_update_msi_mapping(root);
> break;
> - }
>
> case DESIGNWARE_PCIE_MSI_INTR0_MASK:
> root->msi.intr[0].mask = val;
> --
> 2.20.1
next prev parent reply other threads:[~2019-06-18 1:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-16 1:38 [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes Andrey Smirnov
2019-04-16 1:38 ` Andrey Smirnov
2019-04-16 1:38 ` [Qemu-devel] [PATCH 1/5] i.mx7d: Add no-op/unimplemented APBH DMA module Andrey Smirnov
2019-04-16 1:38 ` Andrey Smirnov
2019-06-18 5:15 ` Philippe Mathieu-Daudé
2019-04-16 1:38 ` [Qemu-devel] [PATCH 2/5] i.mx7d: Add no-op/unimplemented PCIE PHY IP block Andrey Smirnov
2019-04-16 1:38 ` Andrey Smirnov
2019-06-18 5:20 ` Philippe Mathieu-Daudé
2019-04-16 1:39 ` [Qemu-devel] [PATCH 3/5] pci: designware: Update MSI mapping unconditionally Andrey Smirnov
2019-04-16 1:39 ` Andrey Smirnov
2019-06-18 1:26 ` Michael S. Tsirkin [this message]
2019-07-01 11:56 ` Peter Maydell
2019-04-16 1:39 ` [Qemu-devel] [PATCH 4/5] pci: designware: Update MSI mapping when MSI address changes Andrey Smirnov
2019-04-16 1:39 ` Andrey Smirnov
2019-06-18 1:26 ` Michael S. Tsirkin
2019-07-01 11:56 ` Peter Maydell
2019-04-16 1:39 ` [Qemu-devel] [PATCH 5/5] i.mx7d: pci: Update PCI IRQ mapping to match HW Andrey Smirnov
2019-04-16 1:39 ` Andrey Smirnov
2019-07-01 12:01 ` Peter Maydell
2019-06-18 0:27 ` [Qemu-devel] [PATCH 0/5] Various i.MX7 fixes Andrey Smirnov
2019-07-01 12:12 ` Peter Maydell
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