[Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and fixing issues

[Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and fixing issues

[David Brenken]

From: David Brenken <david.brenken@efs-auto.de>

Hello everyone,

as discussed here is the second version of the patchset.
- We changed the implementation of the RRPW_INSERT to make use of 
tcg_gen_deposit_tl.
- We added more information of the implementation of QSEED in the code
and changed parts of the implementation.
- We do only sync ctx.hflags with tb->flags.

Best regards

David

Andreas Konopik (1):
  tricore: add QSEED instruction

David Brenken (3):
  tricore: add FTOIZ instruction
  tricore: add UTOF instruction
  tricore: fix RRPW_INSERT instruction

Georg Hofstetter (1):
  tricore: reset DisasContext before generating code

 target/tricore/fpu_helper.c | 126 ++++++++++++++++++++++++++++++++++++
 target/tricore/helper.h     |   3 +
 target/tricore/translate.c  |  14 +++-
 3 files changed, 141 insertions(+), 2 deletions(-)

-- 
2.22.0.windows.1

[Qemu-devel] [PATCH v2 1/5] tricore: add FTOIZ instruction

[David Brenken]

From: David Brenken <david.brenken@efs-auto.de>

Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/tricore/fpu_helper.c | 25 +++++++++++++++++++++++++
 target/tricore/helper.h     |  1 +
 target/tricore/translate.c  |  3 +++
 3 files changed, 29 insertions(+)

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index d8a6c0d25b..f079d9e939 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -303,6 +303,31 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
     return (uint32_t)f_result;
 }
 
+uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_arg = make_float32(arg);
+    uint32_t result;
+    int32_t flags;
+
+    result = float32_to_int32_round_to_zero(f_arg, &env->fp_status);
+
+    flags = f_get_excp_flags(env);
+    if (flags & float_flag_invalid) {
+        flags &= ~float_flag_inexact;
+        if (float32_is_any_nan(f_arg)) {
+            result = 0;
+        }
+    }
+
+    if (flags) {
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+
+    return result;
+}
+
 uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg)
 {
     float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index f60e81096b..16b62edf7f 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
+DEF_HELPER_2(ftoiz, i32, env, i32)
 DEF_HELPER_2(ftouz, i32, env, i32)
 DEF_HELPER_2(updfl, void, env, i32)
 /* dvinit */
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 06c4485e55..5e1c4f54b9 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6747,6 +6747,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_UPDFL:
         gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RR_FTOIZ:
+        gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;
     default:
         generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
     }
-- 
2.22.0.windows.1

[Qemu-devel] [PATCH v2 2/5] tricore: add UTOF instruction

[David Brenken]

From: David Brenken <david.brenken@efs-auto.de>

Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
 target/tricore/fpu_helper.c | 16 ++++++++++++++++
 target/tricore/helper.h     |  1 +
 target/tricore/translate.c  |  3 +++
 3 files changed, 20 insertions(+)

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index f079d9e939..432079c8e2 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -303,6 +303,22 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg)
     return (uint32_t)f_result;
 }
 
+uint32_t helper_utof(CPUTriCoreState *env, uint32_t arg)
+{
+    float32 f_result;
+    uint32_t flags;
+
+    f_result = uint32_to_float32(arg, &env->fp_status);
+
+    flags = f_get_excp_flags(env);
+    if (flags) {
+        f_update_psw_flags(env, flags);
+    } else {
+        env->FPU_FS = 0;
+    }
+    return (uint32_t)f_result;
+}
+
 uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg)
 {
     float32 f_arg = make_float32(arg);
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index 16b62edf7f..f1a5cb367e 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -111,6 +111,7 @@ DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
+DEF_HELPER_2(utof, i32, env, i32)
 DEF_HELPER_2(ftoiz, i32, env, i32)
 DEF_HELPER_2(ftouz, i32, env, i32)
 DEF_HELPER_2(updfl, void, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 5e1c4f54b9..bd913d71a1 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6747,6 +6747,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_UPDFL:
         gen_helper_updfl(cpu_env, cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RR_UTOF:
+        gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;
     case OPC2_32_RR_FTOIZ:
         gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
-- 
2.22.0.windows.1

[Qemu-devel] [PATCH v2 3/5] tricore: fix RRPW_INSERT instruction

[David Brenken]

From: David Brenken <david.brenken@efs-auto.de>

Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
---
 target/tricore/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index bd913d71a1..5d4febf1c0 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -7025,9 +7025,9 @@ static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
         }
         break;
     case OPC2_32_RRPW_INSERT:
-        if (pos + width <= 31) {
+        if (pos + width <= 32) {
             tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
-                               width, pos);
+                               pos, width);
         }
         break;
     default:
-- 
2.22.0.windows.1

Re: [Qemu-devel] [PATCH v2 3/5] tricore: fix RRPW_INSERT instruction

[Bastian Koppelmann]

On 6/19/19 9:56 AM, David Brenken wrote:
> From: David Brenken <david.brenken@efs-auto.de>
>
> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
> ---
>   target/tricore/translate.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


Cheers,

Bastian

[Qemu-devel] [PATCH v2 4/5] tricore: add QSEED instruction

[David Brenken]

From: Andreas Konopik <andreas.konopik@efs-auto.de>

Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
---
 target/tricore/fpu_helper.c | 85 +++++++++++++++++++++++++++++++++++++
 target/tricore/helper.h     |  1 +
 target/tricore/translate.c  |  3 ++
 3 files changed, 89 insertions(+)

diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c
index 432079c8e2..a0bbc6a95b 100644
--- a/target/tricore/fpu_helper.c
+++ b/target/tricore/fpu_helper.c
@@ -24,6 +24,7 @@
 
 #define QUIET_NAN 0x7fc00000
 #define ADD_NAN   0x7fc00001
+#define SQRT_NAN  0x7fc00004
 #define DIV_NAN   0x7fc00008
 #define MUL_NAN   0x7fc00002
 #define FPU_FS PSW_USB_C
@@ -32,6 +33,9 @@
 #define FPU_FZ PSW_USB_AV
 #define FPU_FU PSW_USB_SAV
 
+#define float32_sqrt_nan make_float32(SQRT_NAN)
+#define float32_quiet_nan make_float32(QUIET_NAN)
+
 /* we don't care about input_denormal */
 static inline uint8_t f_get_excp_flags(CPUTriCoreState *env)
 {
@@ -166,6 +170,87 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
 
 }
 
+/*
+ * Target TriCore QSEED.F significand Lookup Table
+ *
+ * The QSEED.F output significand depends on the least-significant
+ * exponent bit and the 6 most-significant significand bits.
+ *
+ * IEEE 754 float datatype
+ * partitioned into Sign (S), Exponent (E) and Significand (M):
+ *
+ * S   E E E E E E E E   M M M M M M ...
+ *    |             |               |
+ *    +------+------+-------+-------+
+ *           |              |
+ *          for        lookup table
+ *      calculating     index for
+ *        output E       output M
+ *
+ * This lookup table was extracted by analyzing QSEED output
+ * from the real hardware
+ */
+
+static const uint8_t target_qseed_significand_table[128] = {
+    253, 252, 245, 244, 239, 238, 231, 230, 225, 224, 217, 216,
+    211, 210, 205, 204, 201, 200, 195, 194, 189, 188, 185, 184,
+    179, 178, 175, 174, 169, 168, 165, 164, 161, 160, 157, 156,
+    153, 152, 149, 148, 145, 144, 141, 140, 137, 136, 133, 132,
+    131, 130, 127, 126, 123, 122, 121, 120, 117, 116, 115, 114,
+    111, 110, 109, 108, 103, 102, 99, 98, 93, 92, 89, 88, 83,
+    82, 79, 78, 75, 74, 71, 70, 67, 66, 63, 62, 59, 58, 55,
+    54, 53, 52, 49, 48, 45, 44, 43, 42, 39, 38, 37, 36, 33,
+    32, 31, 30, 27, 26, 25, 24, 23, 22, 19, 18, 17, 16, 15,
+    14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2
+};
+
+uint32_t helper_qseed(CPUTriCoreState *env, uint32_t r1)
+{
+    uint32_t arg1, S, E, M, E_minus_one, m_idx;
+    uint32_t new_E, new_M, new_S, result;
+
+    arg1 = make_float32(r1);
+
+    /* fetch IEEE-754 fields S, E and the uppermost 6-bit of M */
+    S = extract32(arg1, 31, 1);
+    E = extract32(arg1, 23, 8);
+    M = extract32(arg1, 17, 6);
+
+    if (float32_is_any_nan(arg1)) {
+        result = float32_quiet_nan;
+    } else if (float32_is_zero_or_denormal(arg1)) {
+        if (float32_is_neg(arg1)) {
+            result = float32_infinity | (1 << 31);
+        } else {
+            result = float32_infinity;
+        }
+    } else if (float32_is_neg(arg1)) {
+        result = float32_sqrt_nan;
+    } else if (float32_is_infinity(arg1)) {
+        result = float32_zero;
+    } else {
+        E_minus_one = E - 1;
+        m_idx = ((E_minus_one & 1) << 6) | M;
+        new_S = S;
+        new_E = 0xBD - E_minus_one / 2;
+        new_M = target_qseed_significand_table[m_idx];
+
+        result = 0;
+        result = deposit32(result, 31, 1, new_S);
+        result = deposit32(result, 23, 8, new_E);
+        result = deposit32(result, 15, 8, new_M);
+    }
+
+    if (float32_is_any_nan(arg1) || result == float32_sqrt_nan) {
+        env->FPU_FI = 1;
+        env->FPU_FS = 1;
+    } else {
+        env->FPU_FS = 0;
+    }
+
+    return (uint32_t) result;
+}
+
 uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
 {
     uint32_t flags;
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
index f1a5cb367e..b64780c37d 100644
--- a/target/tricore/helper.h
+++ b/target/tricore/helper.h
@@ -109,6 +109,7 @@ DEF_HELPER_3(fdiv, i32, env, i32, i32)
 DEF_HELPER_4(fmadd, i32, env, i32, i32, i32)
 DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
 DEF_HELPER_3(fcmp, i32, env, i32, i32)
+DEF_HELPER_2(qseed, i32, env, i32)
 DEF_HELPER_2(ftoi, i32, env, i32)
 DEF_HELPER_2(itof, i32, env, i32)
 DEF_HELPER_2(utof, i32, env, i32)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 5d4febf1c0..b3bfb3ca51 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -6750,6 +6750,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
     case OPC2_32_RR_UTOF:
         gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
+    case OPC2_32_RR_QSEED_F:
+        gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
+        break;				
     case OPC2_32_RR_FTOIZ:
         gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]);
         break;
-- 
2.22.0.windows.1

Re: [Qemu-devel] [PATCH v2 4/5] tricore: add QSEED instruction

[Bastian Koppelmann]

On 6/19/19 9:56 AM, David Brenken wrote:
> +
> +        result = 0;
> +        result = deposit32(result, 31, 1, new_S);
> +        result = deposit32(result, 23, 8, new_E);
> +        result = deposit32(result, 15, 8, new_M);
> +    }
> +
> +    if (float32_is_any_nan(arg1) || result == float32_sqrt_nan) {


You need float32_is_signaling_nan, since only signaling nan raises the 
invalid flag.


> +        env->FPU_FI = 1;

env->FPU_FI = 1 << 31;

See f_update_psw_flags(). FPU_FI  and PSW_V are the same and we defined 
bit 31 as the V bit for optimization purposes.

Cheers,

Bastian

Re: [Qemu-devel] [PATCH v2 4/5] tricore: add QSEED instruction

[Konopik, Andreas (EFS-GH2)]

Hi Bastian,

allright thank you. A fix is already on the way.

Best regards,

Andreas 

> -----Ursprüngliche Nachricht-----
> Von: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Gesendet: Mittwoch, 19. Juni 2019 14:25
> An: David Brenken <david.brenken@efs-auto.org>; qemu-devel@nongnu.org
> Cc: Biermanski, Lars (EFS-GH3) <lars.biermanski@efs-auto.de>; Hofstetter,
> Georg (EFS-GH2) <Georg.Hofstetter@efs-auto.de>; Brenken, David (EFS-GH2)
> <david.brenken@efs-auto.de>; Rasche, Robert (EFS-GH2) <robert.rasche@efs-
> auto.de>; Konopik, Andreas (EFS-GH2) <andreas.konopik@efs-auto.de>
> Betreff: Re: [Qemu-devel] [PATCH v2 4/5] tricore: add QSEED instruction
> 
> 
> On 6/19/19 9:56 AM, David Brenken wrote:
> > +
> > +        result = 0;
> > +        result = deposit32(result, 31, 1, new_S);
> > +        result = deposit32(result, 23, 8, new_E);
> > +        result = deposit32(result, 15, 8, new_M);
> > +    }
> > +
> > +    if (float32_is_any_nan(arg1) || result == float32_sqrt_nan) {
> 
> 
> You need float32_is_signaling_nan, since only signaling nan raises the invalid
> flag.
> 
> 
> > +        env->FPU_FI = 1;
> 
> env->FPU_FI = 1 << 31;
> 
> See f_update_psw_flags(). FPU_FI  and PSW_V are the same and we defined
> bit 31 as the V bit for optimization purposes.
> 
> Cheers,
> 
> Bastian

[Qemu-devel] [PATCH v2 5/5] tricore: reset DisasContext before generating code

[David Brenken]

From: Georg Hofstetter <georg.hofstetter@efs-auto.de>

Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
Signed-off-by: David Brenken <david.brenken@efs-auto.de>
Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
---
 target/tricore/translate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index b3bfb3ca51..8f90c76d35 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8806,6 +8806,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
     target_ulong pc_start;
     int num_insns = 0;
 
+    memset(&ctx, 0x00, sizeof(DisasContext));
     pc_start = tb->pc;
     ctx.pc = pc_start;
     ctx.saved_pc = -1;
-- 
2.22.0.windows.1

Re: [Qemu-devel] [PATCH v2 5/5] tricore: reset DisasContext before generating code

[Bastian Koppelmann]

On 6/19/19 9:56 AM, David Brenken wrote:
> From: Georg Hofstetter <georg.hofstetter@efs-auto.de>
>
> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
> ---
>   target/tricore/translate.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index b3bfb3ca51..8f90c76d35 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -8806,6 +8806,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
>       target_ulong pc_start;
>       int num_insns = 0;
>   
> +    memset(&ctx, 0x00, sizeof(DisasContext));
>       pc_start = tb->pc;
>       ctx.pc = pc_start;
>       ctx.saved_pc = -1;

Still the old patch. Did you make a rebase mistake? :)

Cheers,

Bastian

Re: [Qemu-devel] [PATCH v2 5/5] tricore: reset DisasContext before generating code

[Brenken, David (EFS-GH2)]

Ah. You are right. 
I will fix this one within the third version.

Best regards

David

-----Ursprüngliche Nachricht-----
Von: Bastian Koppelmann [mailto:kbastian@mail.uni-paderborn.de] 
Gesendet: Mittwoch, 19. Juni 2019 14:26
An: David Brenken <david.brenken@efs-auto.org>; qemu-devel@nongnu.org
Cc: Biermanski, Lars (EFS-GH3) <lars.biermanski@efs-auto.de>; Hofstetter, Georg (EFS-GH2) <Georg.Hofstetter@efs-auto.de>; Brenken, David (EFS-GH2) <david.brenken@efs-auto.de>; Rasche, Robert (EFS-GH2) <robert.rasche@efs-auto.de>; Konopik, Andreas (EFS-GH2) <andreas.konopik@efs-auto.de>
Betreff: Re: [Qemu-devel] [PATCH v2 5/5] tricore: reset DisasContext before generating code


On 6/19/19 9:56 AM, David Brenken wrote:
> From: Georg Hofstetter <georg.hofstetter@efs-auto.de>
>
> Signed-off-by: Andreas Konopik <andreas.konopik@efs-auto.de>
> Signed-off-by: David Brenken <david.brenken@efs-auto.de>
> Signed-off-by: Georg Hofstetter <georg.hofstetter@efs-auto.de>
> Signed-off-by: Robert Rasche <robert.rasche@efs-auto.de>
> Signed-off-by: Lars Biermanski <lars.biermanski@efs-auto.de>
> ---
>   target/tricore/translate.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c 
> index b3bfb3ca51..8f90c76d35 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -8806,6 +8806,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
>       target_ulong pc_start;
>       int num_insns = 0;
>   
> +    memset(&ctx, 0x00, sizeof(DisasContext));
>       pc_start = tb->pc;
>       ctx.pc = pc_start;
>       ctx.saved_pc = -1;

Still the old patch. Did you make a rebase mistake? :)

Cheers,

Bastian

Re: [Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and fixing issues

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190619075643.10048-1-david.brenken@efs-auto.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and fixing issues
Type: series
Message-id: 20190619075643.10048-1-david.brenken@efs-auto.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag]               patchew/20190619075643.10048-1-david.brenken@efs-auto.org -> patchew/20190619075643.10048-1-david.brenken@efs-auto.org
Switched to a new branch 'test'
b4315e0b64 tricore: reset DisasContext before generating code
915f96578d tricore: add QSEED instruction
cf97b82189 tricore: fix RRPW_INSERT instruction
a3170a6c41 tricore: add UTOF instruction
7366542cc6 tricore: add FTOIZ instruction

=== OUTPUT BEGIN ===
1/5 Checking commit 7366542cc639 (tricore: add FTOIZ instruction)
2/5 Checking commit a3170a6c41b8 (tricore: add UTOF instruction)
3/5 Checking commit cf97b8218918 (tricore: fix RRPW_INSERT instruction)
4/5 Checking commit 915f96578db6 (tricore: add QSEED instruction)
ERROR: trailing whitespace
#146: FILE: target/tricore/translate.c:6755:
+        break;^I^I^I^I$

ERROR: code indent should never use tabs
#146: FILE: target/tricore/translate.c:6755:
+        break;^I^I^I^I$

total: 2 errors, 0 warnings, 119 lines checked

Patch 4/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

5/5 Checking commit b4315e0b64ed (tricore: reset DisasContext before generating code)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190619075643.10048-1-david.brenken@efs-auto.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and fixing issues

[no-reply]

Patchew URL: https://patchew.org/QEMU/20190619075643.10048-1-david.brenken@efs-auto.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v2 0/5] tricore: adding new instructions and fixing issues
Type: series
Message-id: 20190619075643.10048-1-david.brenken@efs-auto.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 t [tag update]            patchew/20190619075643.10048-1-david.brenken@efs-auto.org -> patchew/20190619075643.10048-1-david.brenken@efs-auto.org
Switched to a new branch 'test'
cef0cc9a23 tricore: reset DisasContext before generating code
7961721b61 tricore: add QSEED instruction
c1173a9492 tricore: fix RRPW_INSERT instruction
29d6aeb64c tricore: add UTOF instruction
f0b753a6c2 tricore: add FTOIZ instruction

=== OUTPUT BEGIN ===
1/5 Checking commit f0b753a6c2da (tricore: add FTOIZ instruction)
2/5 Checking commit 29d6aeb64c9b (tricore: add UTOF instruction)
3/5 Checking commit c1173a949230 (tricore: fix RRPW_INSERT instruction)
4/5 Checking commit 7961721b6133 (tricore: add QSEED instruction)
ERROR: trailing whitespace
#146: FILE: target/tricore/translate.c:6755:
+        break;^I^I^I^I$

ERROR: code indent should never use tabs
#146: FILE: target/tricore/translate.c:6755:
+        break;^I^I^I^I$

total: 2 errors, 0 warnings, 119 lines checked

Patch 4/5 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

5/5 Checking commit cef0cc9a2327 (tricore: reset DisasContext before generating code)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190619075643.10048-1-david.brenken@efs-auto.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com