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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id l1sm646781wmg.13.2019.06.24.15.28.58 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Mon, 24 Jun 2019 15:28:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 25 Jun 2019 00:28:44 +0200 Message-Id: <20190624222844.26584-11-f4bug@amsat.org> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190624222844.26584-1-f4bug@amsat.org> References: <20190624222844.26584-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [RFC PATCH 10/10] hw/pci-host/gt64120: Clean the decoded address space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Artyom Tarasenko , Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The SysAd bus is split in various address spaces. Declare the different regions separately, this helps a lot while tracing different access while debugging. We also add the PCI1 ranges. See 'GT-64120A System Controller' datasheet Rev, 1.1, "Table 15: CPU and Device Decoder Default Address Mapping" Signed-off-by: Philippe Mathieu-Daudé --- While this device is modelled toward the Malta board, it is generic. --- hw/mips/mips_malta.c | 6 ------ hw/pci-host/gt64120.c | 19 +++++++++++++++++++ 2 files changed, 19 insertions(+), 6 deletions(-) diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 97f8ffbf1b..d6e4a0dad9 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -53,7 +53,6 @@ #include "sysemu/qtest.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/misc/empty_slot.h" #include "sysemu/kvm.h" #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" @@ -1209,11 +1208,6 @@ void mips_malta_init(MachineState *machine) DeviceState *dev = qdev_create(NULL, TYPE_MIPS_MALTA); MaltaState *s = MIPS_MALTA(dev); - /* The whole address space decoded by the GT-64120A doesn't generate - exception when accessing invalid memory. Create an empty slot to - emulate this feature. */ - empty_slot_init("gt64120-ad", 0x00000000, 0x20000000); - qdev_init_nofail(dev); /* create CPU */ diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 5209038ee5..6eaa571994 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -31,6 +31,8 @@ #include "hw/pci/pci_host.h" #include "hw/i386/pc.h" #include "exec/address-spaces.h" +#include "hw/misc/empty_slot.h" +#include "hw/misc/unimp.h" #include "trace.h" #define GT_REGS (0x1000 >> 2) @@ -1206,6 +1208,23 @@ PCIBus *gt64120_create(qemu_irq *pic, bool target_is_bigendian) "isd-mem", 0x1000); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); + + create_unimplemented_device("gt64120_i2o", 0x14000000, 256); + + empty_slot_init("SCS0", 0x00000000, 8 * MiB); + empty_slot_init("SCS1", 0x00800000, 8 * MiB); + empty_slot_init("SCS2", 0x01000000, 8 * MiB); + empty_slot_init("SCS3", 0x01800000, 8 * MiB); + empty_slot_init("CS0", 0x1c000000, 8 * MiB); + empty_slot_init("CS1", 0x1c800000, 8 * MiB); + empty_slot_init("CS2", 0x1d000000, 32 * MiB); + empty_slot_init("CS3", 0x1f000000, 12 * MiB); + empty_slot_init("BootCS", 0x1fc00000, 4 * MiB); + + create_unimplemented_device("pci1-io", 0x20000000, 32 * MiB); + empty_slot_init("pci1-mem0", 0x22000000, 32 * MiB); + empty_slot_init("pci1-mem1", 0x24000000, 32 * MiB); + return phb->bus; } -- 2.19.1