* [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension
@ 2019-06-25 10:07 Palmer Dabbelt
2019-06-25 15:20 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: Palmer Dabbelt @ 2019-06-25 10:07 UTC (permalink / raw)
To: Alistair Francis; +Cc: Palmer Dabbelt, qemu-riscv, qemu-devel
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 5 +++++
3 files changed, 7 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bbad39a337b3..915b9e77df33 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
+ DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ba551cd3082c..0adb307f3298 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -224,6 +224,7 @@ typedef struct RISCVCPU {
bool ext_u;
bool ext_counters;
bool ext_ifencei;
+ bool ext_icsr;
char *priv_spec;
char *user_spec;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index de67741f3648..ff988917b995 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
{
int ret;
target_ulong old_value;
+ RISCVCPU *cpu = env_archcpu(env);
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
@@ -803,6 +804,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
}
#endif
+ /* ensure the CSR extension is enabled. */
+ if (!cpu->cfg.ext_icsr)
+ return -1;
+
/* check predicate */
if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
return -1;
--
2.21.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension
2019-06-25 10:07 [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension Palmer Dabbelt
@ 2019-06-25 15:20 ` Alistair Francis
2019-06-26 6:07 ` Palmer Dabbelt
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2019-06-25 15:20 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: open list:RISC-V, Alistair Francis,
qemu-devel@nongnu.org Developers
On Tue, Jun 25, 2019 at 3:09 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> The various CSR instructions have been split out of the base ISA as part
> of the ratification process. This patch adds a Zicsr argument, which
> disables all the CSR instructions.
>
> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> target/riscv/csr.c | 5 +++++
> 3 files changed, 7 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index bbad39a337b3..915b9e77df33 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index ba551cd3082c..0adb307f3298 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -224,6 +224,7 @@ typedef struct RISCVCPU {
> bool ext_u;
> bool ext_counters;
> bool ext_ifencei;
> + bool ext_icsr;
>
> char *priv_spec;
> char *user_spec;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index de67741f3648..ff988917b995 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> {
> int ret;
> target_ulong old_value;
> + RISCVCPU *cpu = env_archcpu(env);
>
> /* check privileges and return -1 if check fails */
> #if !defined(CONFIG_USER_ONLY)
> @@ -803,6 +804,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> }
> #endif
>
> + /* ensure the CSR extension is enabled. */
> + if (!cpu->cfg.ext_icsr)
> + return -1;
QEMU style include curly braces around a single line if. Plus I think
it makes it less error prone. Can you add braces?
After that:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> +
> /* check predicate */
> if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
> return -1;
> --
> 2.21.0
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension
2019-06-25 15:20 ` Alistair Francis
@ 2019-06-26 6:07 ` Palmer Dabbelt
0 siblings, 0 replies; 3+ messages in thread
From: Palmer Dabbelt @ 2019-06-26 6:07 UTC (permalink / raw)
To: alistair23; +Cc: qemu-riscv, Alistair Francis, qemu-devel
On Tue, 25 Jun 2019 08:20:55 PDT (-0700), alistair23@gmail.com wrote:
> On Tue, Jun 25, 2019 at 3:09 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>>
>> The various CSR instructions have been split out of the base ISA as part
>> of the ratification process. This patch adds a Zicsr argument, which
>> disables all the CSR instructions.
>>
>> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
>> ---
>> target/riscv/cpu.c | 1 +
>> target/riscv/cpu.h | 1 +
>> target/riscv/csr.c | 5 +++++
>> 3 files changed, 7 insertions(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index bbad39a337b3..915b9e77df33 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -442,6 +442,7 @@ static Property riscv_cpu_properties[] = {
>> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
>> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>> + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
>> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index ba551cd3082c..0adb307f3298 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -224,6 +224,7 @@ typedef struct RISCVCPU {
>> bool ext_u;
>> bool ext_counters;
>> bool ext_ifencei;
>> + bool ext_icsr;
>>
>> char *priv_spec;
>> char *user_spec;
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index de67741f3648..ff988917b995 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -793,6 +793,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>> {
>> int ret;
>> target_ulong old_value;
>> + RISCVCPU *cpu = env_archcpu(env);
>>
>> /* check privileges and return -1 if check fails */
>> #if !defined(CONFIG_USER_ONLY)
>> @@ -803,6 +804,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
>> }
>> #endif
>>
>> + /* ensure the CSR extension is enabled. */
>> + if (!cpu->cfg.ext_icsr)
>> + return -1;
>
> QEMU style include curly braces around a single line if. Plus I think
> it makes it less error prone. Can you add braces?
>
> After that:
>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks.
>
> Alistair
>
>> +
>> /* check predicate */
>> if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
>> return -1;
>> --
>> 2.21.0
>>
>>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-06-26 6:09 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-06-25 10:07 [Qemu-devel] [PATCH] RISC-V: Add support for the Zicsr extension Palmer Dabbelt
2019-06-25 15:20 ` Alistair Francis
2019-06-26 6:07 ` Palmer Dabbelt
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).