Re: [Qemu-devel] RFC: Why does target/m68k RTE insn. use gen_exception

[Lucien Murray-Pitts <lucienmp.qemu@gmail.com>]

On Thu, Jun 27, 2019 at 07:09:39PM +0200, Richard Henderson wrote:
> On 6/27/19 3:22 PM, Lucien Anti-Spam wrote:
> > Hi Laurent / Richard,
> > (resent email )
> > 
> > Does anyone have any knowledge why
> >     gen_exception(s, s->base.pc_next, EXCP_RTE);
> > 
> > is generated for "RTE" instruction, where as the "RTS" goes a gen_jmp?
> > ( note see target/m68k/translate.c in functions DISAS_INSN(rte) and DISAS_INSN(rts)
> 
> History, it would seem.  Paul Brook implemented it that way in 2007.

Ok, thank you I wanted to make sure RTE wasnt being one like this as a special case.

> 
> I think that it should not be implemented as an exception.  It should be a call
> to one of two different helpers (cf and m68k), followed by either a normal exit
> to main loop (to recognize the new interrupt state) or a debug exception.
> 
> This sort of modification should be fairly easy to perform, if you have the time.
> 

The original way of handling it was causing single step to malfunction, I dont
rightly know why but the effect was that step would step twice and end up
inside the ISR function again OR just stepping past the RTE as if it didnt
exist.

I have made a quick hack to implement it the way you suggest and confirm that
works better.

HOWEVER, the "return" address is the instruction that causes the exception.
So it immediately does return to the ISR.

This is a different issue, but I think interrelated to the original problem.

Further single stepping INTO the failing instruction results in ending up
at the ISR +1 instruction

I will look at these but so far a little lost on the why for of them.

Cheers,
Luc

> 
> r~