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[69.222.133.165]) by smtp.gmail.com with ESMTPSA id k126sm1108564ywf.36.2019.06.30.21.35.52 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Sun, 30 Jun 2019 21:35:52 -0700 (PDT) From: Jan Bobek To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 00:35:22 -0400 Message-Id: <20190701043536.26019-1-jan.bobek@gmail.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::c44 Subject: [Qemu-devel] [RISU RFC PATCH v2 00/14] Support for generating x86 MMX/SSE/AVX test images X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jan Bobek , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a v2 of the patch series first posted in [1]. This version also implements the VEX prefix, hence all SIMD extensions up to AVX2 are supported. Notable exceptions are LDMXCSR (cannot constrain memory contents yet) and all forms of VGATHER (VSIB not implemented). Note that this is still not the final version; I am planning to implement randomization of VSIB to test VGATHER, and improve the way registers are randomized (as discussed in e.g. [2]). Changes since v1: - risugen_common: rewrote insnv to make it clearer, added a comment to randint_constr; - risugen_x86_asm: fixed a typo in rex_encode; - risugen_x86: use more than one opcode in write_mov_reg_imm to optimize space usage; - x86.risu: added all SIMD extensnions up to AVX2. References: 1. https://lists.nongnu.org/archive/html/qemu-devel/2019-06/msg04123.html 2. https://lists.nongnu.org/archive/html/qemu-devel/2019-06/msg06489.html Jan Bobek (14): risugen_common: add insnv, randint_constr, rand_fill risugen_x86_asm: add module risugen_x86_emit: add module risugen_x86: add module risugen: allow all byte-aligned instructions x86.risu: add MMX instructions x86.risu: add SSE instructions x86.risu: add SSE2 instructions x86.risu: add SSE3 instructions x86.risu: add SSSE3 instructions x86.risu: add SSE4.1 and SSE4.2 instructions x86.risu: add AES and PCLMULQDQ instructions x86.risu: add AVX instructions x86.risu: add AVX2 instructions risugen | 15 +- risugen_common.pm | 107 ++++- risugen_x86.pm | 498 +++++++++++++++++++++ risugen_x86_asm.pm | 252 +++++++++++ risugen_x86_emit.pm | 91 ++++ x86.risu | 1026 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 1977 insertions(+), 12 deletions(-) create mode 100644 risugen_x86.pm create mode 100644 risugen_x86_asm.pm create mode 100644 risugen_x86_emit.pm create mode 100644 x86.risu -- 2.20.1