From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@sifive.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3
Date: Mon, 1 Jul 2019 13:40:29 +0100 [thread overview]
Message-ID: <20190701134029.00004b97@huawei.com> (raw)
In-Reply-To: <CAKmqyKP1c5GHKaDuOvu11UtCwnrUosxTtoDAeW7GOS=s+h27aw@mail.gmail.com>
On Fri, 28 Jun 2019 09:12:45 -0700
Alistair Francis <alistair23@gmail.com> wrote:
> On Fri, Jun 28, 2019 at 2:47 AM Jonathan Cameron
> <jonathan.cameron@huawei.com> wrote:
> >
> > On Thu, 27 Jun 2019 08:20:10 -0700
> > Palmer Dabbelt <palmer@sifive.com> wrote:
> >
> > > From: Alistair Francis <alistair.francis@wdc.com>
> > >
> > > Add OpenSBI version 0.3 as a git submodule and as a prebult binary.
> > >
> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > > Tested-by: Bin Meng <bmeng.cn@gmail.com>
> > > Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
> >
> > I sent a late bug report on this one.. Hence posting here as well
> > to make sure it doesn't fall through the cracks!
> >
> > Right now you can't actually build the opensbi64-virt firmware
> > due to cut and paste error in the Makefile.
>
> Ah, thanks for the bug report.
>
> @Palmer Dabbelt I'm just going to send you a fixup commit. Can you
> apply it to your tree and send a PRv2?
>
> >
> > As a side note, I hit this because OpenSBI 0.3 is resulting in a login
> > loop on a debian test image and the current upstream isn't. I haven't
> > debugged yet, but someone else may hit that problem.
>
> Unfortunately OpenSBI 0.3 is a little old now, in saying that I didn't
> know there are bugs in it? Which kernel are you using?
Mainline 5.2.0-rc5.
Just in case I also checked 5.2.0-rc7
I tried doing an odd git bisect with good and bad reversed to figure out
what fixed the problem, but boot wedged at "Run /sbin/init as init process."
The wedge was bisected to:
4e2cd47820 ("lib: Flush everything when remote TLB flush range is too large")
Which the patch correctly identifies as a problem introduced this kernel cycle.
5.2-rc1.
So on that basis alone I'd suggest we want to move to a more recent openSBI
asap, after all the 5.2 kernel will be out in a week or so.
I'm a bit short on time (flight to catch), so haven't pushed that fix that
far back in the tree yet in order to figure what is causing the login loop.
Won't have access to relevant build machines until Wednesday.
That patch cherry-picked on lib: Optimize TLB flush IPIs
seems fine, so it is before that point...
Passing that point would require real effort though as the two patches
are changing the same code.
So I had a go from the other end (0.3) to see if it was fixed quickly.
Ran out of time, but at
"firmware: Reset all registers and flush the icache" it superficially all
seems to be working with no TLB related hang, or login loop.
The login loop is present in firmware: Add a barrier instruction for wait for boot hart.
Will see if I can pin it down fully later in the week.
Thanks,
Jonathan
>
> Alistair
>
> >
> > Thanks,
> >
> > Jonathan
> >
> > > diff --git a/roms/Makefile b/roms/Makefile
> > > index 078d3fb70563..562ed726fd6b 100644
> > > --- a/roms/Makefile
> > > +++ b/roms/Makefile
> > > @@ -37,6 +37,8 @@ find-cross-prefix = $(subst gcc,,$(notdir $(call find-cross-gcc,$(1))))
> > > powerpc64_cross_prefix := $(call find-cross-prefix,powerpc64)
> > > powerpc_cross_prefix := $(call find-cross-prefix,powerpc)
> > > x86_64_cross_prefix := $(call find-cross-prefix,x86_64)
> > > +riscv32_cross_prefix := $(call find-cross-prefix,riscv32)
> > > +riscv64_cross_prefix := $(call find-cross-prefix,riscv64)
> > >
> > > # tag our seabios builds
> > > SEABIOS_EXTRAVERSION="-prebuilt.qemu.org"
> > > @@ -52,18 +54,21 @@ EDK2_EFIROM = edk2/BaseTools/Source/C/bin/EfiRom
> > > default:
> > > @echo "nothing is build by default"
> > > @echo "available build targets:"
> > > - @echo " bios -- update bios.bin (seabios)"
> > > - @echo " vgabios -- update vgabios binaries (seabios)"
> > > - @echo " sgabios -- update sgabios binaries"
> > > - @echo " pxerom -- update nic roms (bios only)"
> > > - @echo " efirom -- update nic roms (bios+efi)"
> > > - @echo " slof -- update slof.bin"
> > > - @echo " skiboot -- update skiboot.lid"
> > > - @echo " u-boot.e500 -- update u-boot.e500"
> > > - @echo " u-boot.sam460 -- update u-boot.sam460"
> > > - @echo " efi -- update UEFI (edk2) platform firmware"
> > > - @echo " clean -- delete the files generated by the previous" \
> > > - "build targets"
> > > + @echo " bios -- update bios.bin (seabios)"
> > > + @echo " vgabios -- update vgabios binaries (seabios)"
> > > + @echo " sgabios -- update sgabios binaries"
> > > + @echo " pxerom -- update nic roms (bios only)"
> > > + @echo " efirom -- update nic roms (bios+efi)"
> > > + @echo " slof -- update slof.bin"
> > > + @echo " skiboot -- update skiboot.lid"
> > > + @echo " u-boot.e500 -- update u-boot.e500"
> > > + @echo " u-boot.sam460 -- update u-boot.sam460"
> > > + @echo " efi -- update UEFI (edk2) platform firmware"
> > > + @echo " opensbi32-virt -- update OpenSBI for 32-bit virt machine"
> > > + @echo " opensbi64-virt -- update OpenSBI for 64-bit virt machine"
> > > + @echo " opensbi64-sifive_u -- update OpenSBI for 64-bit sifive_u machine"
> > > + @echo " clean -- delete the files generated by the previous" \
> > > + "build targets"
> > >
> > > bios: build-seabios-config-seabios-128k build-seabios-config-seabios-256k
> > > cp seabios/builds/seabios-128k/bios.bin ../pc-bios/bios.bin
> > > @@ -162,6 +167,24 @@ skiboot:
> > > efi: edk2-basetools
> > > $(MAKE) -f Makefile.edk2
> > >
> > > +opensbi32-virt:
> > > + $(MAKE) -C opensbi \
> > > + CROSS_COMPILE=$(riscv32_cross_prefix) \
> > > + PLATFORM="qemu/virt"
> > > + cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv32-virt-fw_jump.bin
> > > +
> > > +opensbi64-virt:
> > > + $(MAKE) -C opensbi \
> > > + CROSS_COMPILE=$(riscv64_cross_prefix) \
> > > + PLATFORM="qemu/virt"
> > > + cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-virt-fw_jump.bin
> > > +
> > > +opensbi64-virt:
> >
> > Cut and paste buglet. opensbi64-sifive_u
> >
> > > + $(MAKE) -C opensbi \
> > > + CROSS_COMPILE=$(riscv64_cross_prefix) \
> > > + PLATFORM="qemu/sifive_u"
> > > + cp opensbi/build/platform/qemu/virt/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
> > > +
> > > clean:
> > > rm -rf seabios/.config seabios/out seabios/builds
> > > $(MAKE) -C sgabios clean
> > > @@ -173,3 +196,4 @@ clean:
> > > $(MAKE) -C u-boot-sam460ex distclean
> > > $(MAKE) -C skiboot clean
> > > $(MAKE) -f Makefile.edk2 clean
> > > + $(MAKE) -C opensbi clean
> > > diff --git a/roms/opensbi b/roms/opensbi
> > > new file mode 160000
> > > index 000000000000..ca20ac0cd4c0
> > > --- /dev/null
> > > +++ b/roms/opensbi
> > > @@ -0,0 +1 @@
> > > +Subproject commit ca20ac0cd4c099006d4eea4d9ac7bd7b58e2ae0f
> >
> >
> >
next prev parent reply other threads:[~2019-07-01 12:48 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-27 15:19 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 02/34] sifive_prci: Read and write PRCI registers Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 03/34] target/riscv: Fix PMP range boundary address bug Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 08/34] RISC-V: Check PMP during Page Table Walks Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size Palmer Dabbelt
2019-06-27 17:44 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-06-27 18:23 ` Richard Henderson
2019-07-08 12:46 ` Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 13/34] target/riscv: Restructure deprecatd CPUs Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0 Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 15/34] target/riscv: Add the mcountinhibit CSR Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1 Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 18/34] target/riscv: Require either I or E base extension Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 19/34] target/riscv: Remove user version information Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 21/34] RISC-V: Add support for the Zifencei extension Palmer Dabbelt
2019-06-27 15:19 ` [Qemu-devel] [PULL 22/34] RISC-V: Add support for the Zicsr extension Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 24/34] RISC-V: Update syscall list for 32-bit support Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 25/34] riscv: virt: Add cpu-topology DT node Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 30/34] hw/riscv: Split out the boot functions Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 31/34] hw/riscv: Add support for loading a firmware Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 32/34] hw/riscv: Extend the kernel loading support Palmer Dabbelt
2019-06-27 15:20 ` [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3 Palmer Dabbelt
2019-06-28 9:46 ` Jonathan Cameron
2019-06-28 16:12 ` Alistair Francis
2019-06-28 17:10 ` Palmer Dabbelt
2019-07-01 12:40 ` Jonathan Cameron [this message]
2019-07-01 13:23 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-07-01 16:39 ` Alistair Francis
2019-07-01 16:54 ` [Qemu-devel] " Peter Maydell
2019-07-01 17:50 ` Alistair Francis
2019-07-01 18:01 ` Peter Maydell
2019-07-01 18:09 ` Alistair Francis
2019-07-01 18:13 ` Peter Maydell
2019-07-01 18:19 ` Alistair Francis
2019-07-02 7:02 ` [Qemu-devel] [Qemu-riscv] " Anup Patel
2019-07-02 4:12 ` [Qemu-devel] " Markus Armbruster
2019-07-02 10:32 ` Paolo Bonzini
2019-07-02 16:07 ` Alistair Francis
2019-07-04 16:00 ` Stefan Hajnoczi
2019-07-04 19:35 ` Alistair Francis
2019-06-27 15:20 ` [Qemu-devel] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware Palmer Dabbelt
-- strict thread matches above, loose matches on Subject: below --
2019-06-28 17:31 [Qemu-devel] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2 Palmer Dabbelt
2019-06-28 17:32 ` [Qemu-devel] [PULL 33/34] roms: Add OpenSBI version 0.3 Palmer Dabbelt
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190701134029.00004b97@huawei.com \
--to=jonathan.cameron@huawei.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=bmeng.cn@gmail.com \
--cc=palmer@sifive.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).