From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78BF6C5B578 for ; Tue, 2 Jul 2019 01:28:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 52C5821473 for ; Tue, 2 Jul 2019 01:28:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 52C5821473 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi7aZ-0007LN-KT for qemu-devel@archiver.kernel.org; Mon, 01 Jul 2019 21:28:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44739) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi3rd-0005Iv-DI for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:29:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi3rc-0008Rg-Ct for qemu-devel@nongnu.org; Mon, 01 Jul 2019 17:29:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36895) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hi3rZ-0008No-DL; Mon, 01 Jul 2019 17:29:25 -0400 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1F18630BBE98; Mon, 1 Jul 2019 19:50:21 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.205.170]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2B6CF379F; Mon, 1 Jul 2019 19:50:17 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 21:49:40 +0200 Message-Id: <20190701194942.10092-7-philmd@redhat.com> In-Reply-To: <20190701194942.10092-1-philmd@redhat.com> References: <20190701194942.10092-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Mon, 01 Jul 2019 19:50:21 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v4 6/8] RFC target/arm: Restrict R and M profiles to TCG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Zhong , Peter Maydell , Andrew Jones , Samuel Ortiz , Rob Bradford , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" KVM is only able to run A profile cpus. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 290ef16e52..a0934a47ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -453,7 +453,9 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) return ret; } =20 -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if (!defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)) \ + && defined(CONFIG_TCG) static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_reque= st) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -1855,8 +1857,6 @@ static void cortex_m0_initfn(Object *obj) cpu->midr =3D 0x410cc200; } =20 -#endif - static void cortex_m3_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2010,6 +2010,8 @@ static void cortex_r5f_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000011; } =20 +#endif + static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -2491,7 +2493,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm1176", .initfn =3D arm1176_initfn }, { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, -#endif .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, .class_init =3D arm_v7m_class_init }, @@ -2501,6 +2502,7 @@ static const ARMCPUInfo arm_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, +#endif { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, --=20 2.20.1