From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A8BC5B578 for ; Tue, 2 Jul 2019 03:07:46 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5A1C5206A2 for ; Tue, 2 Jul 2019 03:07:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5A1C5206A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:47792 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi98z-0006PB-Ke for qemu-devel@archiver.kernel.org; Mon, 01 Jul 2019 23:07:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34206) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hi78w-0002gB-VY for qemu-devel@nongnu.org; Mon, 01 Jul 2019 20:59:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hi78t-0000xA-Hg for qemu-devel@nongnu.org; Mon, 01 Jul 2019 20:59:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37700) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hi78n-0000pX-Bv; Mon, 01 Jul 2019 20:59:25 -0400 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 72DD8FA8CC; Tue, 2 Jul 2019 00:59:24 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-21.brq.redhat.com [10.40.204.21]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 422861001B33; Tue, 2 Jul 2019 00:59:19 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Mon, 1 Jul 2019 21:58:46 -0300 Message-Id: <20190702005912.15905-2-philmd@redhat.com> In-Reply-To: <20190702005912.15905-1-philmd@redhat.com> References: <20190702005912.15905-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 02 Jul 2019 00:59:24 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PULL 01/27] tests/pflash-cfi02: Add test for supported CFI commands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Laurent Vivier , Thomas Huth , Stephen Checkoway , qemu-block@nongnu.org, Max Reitz , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Stephen Checkoway Test the AMD command set for parallel flash chips. This test uses an ARM musicpal board with a pflash drive to test the following list of currently-supported commands. - Autoselect - CFI - Sector erase - Chip erase - Program - Unlock bypass - Reset Signed-off-by: Stephen Checkoway Message-Id: <20190426162624.55977-2-stephen.checkoway@oberlin.edu> Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 [PMD: reworded the patch subject, g_assert_cmpint -> cmphex] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tests/Makefile.include | 2 + tests/pflash-cfi02-test.c | 225 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 227 insertions(+) create mode 100644 tests/pflash-cfi02-test.c diff --git a/tests/Makefile.include b/tests/Makefile.include index db750dd6d0..d02132fb94 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -260,6 +260,7 @@ check-qtest-arm-y +=3D tests/m25p80-test$(EXESUF) check-qtest-arm-y +=3D tests/test-arm-mptimer$(EXESUF) check-qtest-arm-y +=3D tests/boot-serial-test$(EXESUF) check-qtest-arm-y +=3D tests/hexloader-test$(EXESUF) +check-qtest-arm-$(CONFIG_PFLASH_CFI02) +=3D tests/pflash-cfi02-test$(EXE= SUF) =20 check-qtest-aarch64-y =3D tests/numa-test$(EXESUF) check-qtest-aarch64-y +=3D tests/boot-serial-test$(EXESUF) @@ -767,6 +768,7 @@ tests/device-introspect-test$(EXESUF): tests/device-i= ntrospect-test.o tests/rtc-test$(EXESUF): tests/rtc-test.o tests/m48t59-test$(EXESUF): tests/m48t59-test.o tests/hexloader-test$(EXESUF): tests/hexloader-test.o +tests/pflash-cfi02$(EXESUF): tests/pflash-cfi02-test.o tests/endianness-test$(EXESUF): tests/endianness-test.o tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y) tests/rtas-test$(EXESUF): tests/rtas-test.o $(libqos-spapr-obj-y) diff --git a/tests/pflash-cfi02-test.c b/tests/pflash-cfi02-test.c new file mode 100644 index 0000000000..e7e16a8dd8 --- /dev/null +++ b/tests/pflash-cfi02-test.c @@ -0,0 +1,225 @@ +/* + * QTest testcase for parallel flash with AMD command set + * + * Copyright (c) 2019 Stephen Checkoway + * + * This work is licensed under the terms of the GNU GPL, version 2 or la= ter. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +/* + * To test the pflash_cfi02 device, we run QEMU with the musicpal machin= e with + * a pflash drive. This enables us to test some flash configurations, bu= t not + * all. In particular, we're limited to a 16-bit wide flash device. + */ + +#define MP_FLASH_SIZE_MAX (32 * 1024 * 1024) +#define BASE_ADDR (0x100000000ULL - MP_FLASH_SIZE_MAX) + +#define FLASH_WIDTH 2 +#define CFI_ADDR (FLASH_WIDTH * 0x55) +#define UNLOCK0_ADDR (FLASH_WIDTH * 0x5555) +#define UNLOCK1_ADDR (FLASH_WIDTH * 0x2AAA) + +#define CFI_CMD 0x98 +#define UNLOCK0_CMD 0xAA +#define UNLOCK1_CMD 0x55 +#define AUTOSELECT_CMD 0x90 +#define RESET_CMD 0xF0 +#define PROGRAM_CMD 0xA0 +#define SECTOR_ERASE_CMD 0x30 +#define CHIP_ERASE_CMD 0x10 +#define UNLOCK_BYPASS_CMD 0x20 +#define UNLOCK_BYPASS_RESET_CMD 0x00 + +static char image_path[] =3D "/tmp/qtest.XXXXXX"; + +static inline void flash_write(uint64_t byte_addr, uint16_t data) +{ + qtest_writew(global_qtest, BASE_ADDR + byte_addr, data); +} + +static inline uint16_t flash_read(uint64_t byte_addr) +{ + return qtest_readw(global_qtest, BASE_ADDR + byte_addr); +} + +static void unlock(void) +{ + flash_write(UNLOCK0_ADDR, UNLOCK0_CMD); + flash_write(UNLOCK1_ADDR, UNLOCK1_CMD); +} + +static void reset(void) +{ + flash_write(0, RESET_CMD); +} + +static void sector_erase(uint64_t byte_addr) +{ + unlock(); + flash_write(UNLOCK0_ADDR, 0x80); + unlock(); + flash_write(byte_addr, SECTOR_ERASE_CMD); +} + +static void wait_for_completion(uint64_t byte_addr) +{ + /* If DQ6 is toggling, step the clock and ensure the toggle stops. *= / + if ((flash_read(byte_addr) & 0x40) ^ (flash_read(byte_addr) & 0x40))= { + /* Wait for erase or program to finish. */ + clock_step_next(); + /* Ensure that DQ6 has stopped toggling. */ + g_assert_cmphex(flash_read(byte_addr), =3D=3D, flash_read(byte_a= ddr)); + } +} + +static void bypass_program(uint64_t byte_addr, uint16_t data) +{ + flash_write(UNLOCK0_ADDR, PROGRAM_CMD); + flash_write(byte_addr, data); + /* + * Data isn't valid until DQ6 stops toggling. We don't model this as + * writes are immediate, but if this changes in the future, we can w= ait + * until the program is complete. + */ + wait_for_completion(byte_addr); +} + +static void program(uint64_t byte_addr, uint16_t data) +{ + unlock(); + bypass_program(byte_addr, data); +} + +static void chip_erase(void) +{ + unlock(); + flash_write(UNLOCK0_ADDR, 0x80); + unlock(); + flash_write(UNLOCK0_ADDR, SECTOR_ERASE_CMD); +} + +static void test_flash(void) +{ + global_qtest =3D qtest_initf("-M musicpal,accel=3Dqtest " + "-drive if=3Dpflash,file=3D%s,format=3Dra= w,copy-on-read", + image_path); + /* Check the IDs. */ + unlock(); + flash_write(UNLOCK0_ADDR, AUTOSELECT_CMD); + g_assert_cmphex(flash_read(FLASH_WIDTH * 0x0000), =3D=3D, 0x00BF); + g_assert_cmphex(flash_read(FLASH_WIDTH * 0x0001), =3D=3D, 0x236D); + reset(); + + /* Check the erase blocks. */ + flash_write(CFI_ADDR, CFI_CMD); + g_assert_cmphex(flash_read(FLASH_WIDTH * 0x10), =3D=3D, 'Q'); + g_assert_cmphex(flash_read(FLASH_WIDTH * 0x11), =3D=3D, 'R'); + g_assert_cmphex(flash_read(FLASH_WIDTH * 0x12), =3D=3D, 'Y'); + /* Num erase regions. */ + g_assert_cmphex(flash_read(FLASH_WIDTH * 0x2C), >=3D, 1); + uint32_t nb_sectors =3D flash_read(FLASH_WIDTH * 0x2D) + + (flash_read(FLASH_WIDTH * 0x2E) << 8) + 1; + uint32_t sector_len =3D (flash_read(FLASH_WIDTH * 0x2F) << 8) + + (flash_read(FLASH_WIDTH * 0x30) << 16); + reset(); + + /* Erase and program sector. */ + for (uint32_t i =3D 0; i < nb_sectors; ++i) { + uint64_t byte_addr =3D i * sector_len; + sector_erase(byte_addr); + /* Read toggle. */ + uint16_t status0 =3D flash_read(byte_addr); + /* DQ7 is 0 during an erase. */ + g_assert_cmphex(status0 & 0x80, =3D=3D, 0); + uint16_t status1 =3D flash_read(byte_addr); + /* DQ6 toggles during an erase. */ + g_assert_cmphex(status0 & 0x40, !=3D, status1 & 0x40); + /* Wait for erase to complete. */ + clock_step_next(); + /* Ensure DQ6 has stopped toggling. */ + g_assert_cmphex(flash_read(byte_addr), =3D=3D, flash_read(byte_a= ddr)); + /* Now the data should be valid. */ + g_assert_cmphex(flash_read(byte_addr), =3D=3D, 0xFFFF); + + /* Program a bit pattern. */ + program(byte_addr, 0x5555); + g_assert_cmphex(flash_read(byte_addr), =3D=3D, 0x5555); + program(byte_addr, 0xAA55); + g_assert_cmphex(flash_read(byte_addr), =3D=3D, 0x0055); + } + + /* Erase the chip. */ + chip_erase(); + /* Read toggle. */ + uint16_t status0 =3D flash_read(0); + /* DQ7 is 0 during an erase. */ + g_assert_cmphex(status0 & 0x80, =3D=3D, 0); + uint16_t status1 =3D flash_read(0); + /* DQ6 toggles during an erase. */ + g_assert_cmphex(status0 & 0x40, !=3D, status1 & 0x40); + /* Wait for erase to complete. */ + clock_step_next(); + /* Ensure DQ6 has stopped toggling. */ + g_assert_cmphex(flash_read(0), =3D=3D, flash_read(0)); + /* Now the data should be valid. */ + g_assert_cmphex(flash_read(0), =3D=3D, 0xFFFF); + + /* Unlock bypass */ + unlock(); + flash_write(UNLOCK0_ADDR, UNLOCK_BYPASS_CMD); + bypass_program(0, 0x0123); + bypass_program(2, 0x4567); + bypass_program(4, 0x89AB); + /* + * Test that bypass programming, unlike normal programming can use a= ny + * address for the PROGRAM_CMD. + */ + flash_write(6, PROGRAM_CMD); + flash_write(6, 0xCDEF); + wait_for_completion(6); + flash_write(0, UNLOCK_BYPASS_RESET_CMD); + bypass_program(8, 0x55AA); /* Should fail. */ + g_assert_cmphex(flash_read(0), =3D=3D, 0x0123); + g_assert_cmphex(flash_read(2), =3D=3D, 0x4567); + g_assert_cmphex(flash_read(4), =3D=3D, 0x89AB); + g_assert_cmphex(flash_read(6), =3D=3D, 0xCDEF); + g_assert_cmphex(flash_read(8), =3D=3D, 0xFFFF); + + qtest_quit(global_qtest); +} + +static void cleanup(void *opaque) +{ + unlink(image_path); +} + +int main(int argc, char **argv) +{ + int fd =3D mkstemp(image_path); + if (fd =3D=3D -1) { + g_printerr("Failed to create temporary file %s: %s\n", image_pat= h, + strerror(errno)); + exit(EXIT_FAILURE); + } + if (ftruncate(fd, 8 * 1024 * 1024) < 0) { + int error_code =3D errno; + close(fd); + unlink(image_path); + g_printerr("Failed to truncate file %s to 8 MB: %s\n", image_pat= h, + strerror(error_code)); + exit(EXIT_FAILURE); + } + close(fd); + + qtest_add_abrt_handler(cleanup, NULL); + g_test_init(&argc, &argv, NULL); + qtest_add_func("pflash-cfi02", test_flash); + int result =3D g_test_run(); + cleanup(NULL); + return result; +} --=20 2.20.1