From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
qemu-devel@nongnu.org,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PULL v3 36/42] i386: Define -IBRS, -noTSX, -IBRS versions of CPU models
Date: Tue, 2 Jul 2019 12:35:29 -0300 [thread overview]
Message-ID: <20190702153535.9851-37-ehabkost@redhat.com> (raw)
In-Reply-To: <20190702153535.9851-1-ehabkost@redhat.com>
Add versions of CPU models that are equivalent to their -IBRS,
-noTSX and -IBRS variants.
The separate variants will eventually be removed and become
aliases for these CPU versions.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-6-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 186 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index a611c6eae2..99ab6104f4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1851,6 +1851,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Nehalem-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Nehalem-IBRS",
@@ -1907,6 +1921,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Westmere-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Westmere E56xx/L56xx/X56xx (IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Westmere-IBRS",
@@ -1971,6 +1999,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to SandyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "SandyBridge-IBRS",
@@ -2043,6 +2085,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to IvyBridge-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "IvyBridge-IBRS",
@@ -2205,6 +2261,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Haswell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Haswell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "stepping", "1" },
+ { "model-id", "Intel Core Processor (Haswell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Haswell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ /*
+ * Haswell and Haswell-IBRS had stepping=4 in
+ * QEMU 4.0 and older
+ */
+ { "stepping", "4" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Haswell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Haswell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "stepping", "1" },
+ { "model-id",
+ "Intel Core Processor (Haswell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Haswell-IBRS",
@@ -2375,6 +2477,45 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Broadwell)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Broadwell-noTSX */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
+ { /* end of list */ }
+ },
+ },
+ {
+ .version = 3,
+ /* Equivalent to Broadwell-IBRS */
+ .props = (PropValue[]) {
+ /* Restore TSX features removed by -v2 above */
+ { "hle", "on" },
+ { "rtm", "on" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Broadwell, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ {
+ .version = 4,
+ /* Equivalent to Broadwell-noTSX-IBRS */
+ .props = (PropValue[]) {
+ { "hle", "off" },
+ { "rtm", "off" },
+ /* spec-ctrl was already enabled by -v3 above */
+ { "model-id",
+ "Intel Core Processor (Broadwell, no TSX, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Broadwell-IBRS",
@@ -2465,6 +2606,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Core Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Client-IBRS */
+ .props = (PropValue[]) {
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Core Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Client-IBRS",
@@ -2567,6 +2722,23 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_6_EAX_ARAT,
.xlevel = 0x80000008,
.model_id = "Intel Xeon Processor (Skylake)",
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to Skylake-Server-IBRS */
+ .props = (PropValue[]) {
+ /* clflushopt was not added to Skylake-Server-IBRS */
+ /* TODO: add -v3 including clflushopt */
+ { "clflushopt", "off" },
+ { "spec-ctrl", "on" },
+ { "model-id",
+ "Intel Xeon Processor (Skylake, IBRS)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "Skylake-Server-IBRS",
@@ -3082,6 +3254,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
.xlevel = 0x8000001E,
.model_id = "AMD EPYC Processor",
.cache_info = &epyc_cache_info,
+ .versions = (X86CPUVersionDefinition[]) {
+ { .version = 1 },
+ {
+ .version = 2,
+ /* Equivalent to EPYC-IBPB */
+ .props = (PropValue[]) {
+ { "ibpb", "on" },
+ { "model-id",
+ "AMD EPYC Processor (with IBPB)" },
+ { /* end of list */ }
+ }
+ },
+ { /* end of list */ }
+ }
},
{
.name = "EPYC-IBPB",
--
2.18.0.rc1.1.g3f1ff2140
next prev parent reply other threads:[~2019-07-02 16:33 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-02 15:34 [Qemu-devel] [PULL v3 00/42] Machine and x86 queue, 2019-07-02 Eduardo Habkost
2019-07-02 15:34 ` [Qemu-devel] [PULL v3 01/42] hw/boards: Add struct CpuTopology to MachineState Eduardo Habkost
2019-07-02 15:34 ` [Qemu-devel] [PULL v3 02/42] machine: Refactor smp-related call chains to pass MachineState Eduardo Habkost
2019-07-02 15:34 ` [Qemu-devel] [PULL v3 03/42] general: Replace global smp variables with smp machine properties Eduardo Habkost
2019-07-02 15:34 ` [Qemu-devel] [PULL v3 04/42] hw/ppc: Replace global smp variables with machine smp properties Eduardo Habkost
2019-07-02 15:34 ` [Qemu-devel] [PULL v3 05/42] hw/riscv: " Eduardo Habkost
2019-07-02 15:34 ` [Qemu-devel] [PULL v3 06/42] hw/s390x: " Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 07/42] hw/i386: " Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 08/42] hw/arm: " Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 09/42] hw: Replace global smp variables with MachineState for all remaining archs Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 10/42] vl.c: Replace smp global variables with smp machine properties Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 11/42] i386: Add die-level cpu topology to x86CPU on PCMachine Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 12/42] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 13/42] i386/cpu: Consolidate die-id validity in smp context Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 14/42] i386: Update new x86_apicid parsing rules with die_offset support Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 15/42] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size() Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 16/42] machine: show if CLI option '-numa node, mem' is supported in QAPI schema Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 17/42] numa: deprecate 'mem' parameter of '-numa node' option Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 18/42] numa: deprecate implict memory distribution between nodes Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 19/42] hppa: Delete unused hppa_cpu_list() function Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 20/42] target/i386: fix feature check in hyperv-stub.c Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 21/42] deprecate -mem-path fallback to anonymous RAM Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 22/42] i386: Don't print warning if phys-bits was set automatically Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 23/42] i386: Fix signedness of hyperv_spinlock_attempts Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 24/42] i386: make 'hv-spinlocks' a regular uint32 property Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 25/42] x86/cpu: use FeatureWordArray to define filtered_features Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 26/42] i386: Remove unused host_cpudef variable Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 27/42] target/i386: Add CPUID.1F generation support for multi-dies PCMachine Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 28/42] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse() Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 29/42] vl.c: Add -smp, dies=* command line support and update doc Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 30/42] qmp: Add deprecation information to query-machines Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 31/42] i386: Introduce SnowRidge CPU model Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 32/42] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 33/42] i386: Add x-force-features option for testing Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 34/42] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 35/42] i386: Register versioned CPU models Eduardo Habkost
2019-07-02 15:35 ` Eduardo Habkost [this message]
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 37/42] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 38/42] i386: Make unversioned CPU models be aliases Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 39/42] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 40/42] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-07-03 1:16 ` Xiaoyao Li
2019-07-03 18:06 ` Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 41/42] numa: allow memory-less nodes when using memdev as backend Eduardo Habkost
2019-07-02 15:35 ` [Qemu-devel] [PULL v3 42/42] tests: use -numa memdev option in tests instead of legacy 'mem' option Eduardo Habkost
2019-07-02 22:51 ` [Qemu-devel] [PULL v3 00/42] Machine and x86 queue, 2019-07-02 no-reply
2019-07-02 23:19 ` no-reply
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