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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7BE1A1FF8F; Wed, 3 Jul 2019 16:52:44 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 3 Jul 2019 16:52:42 +0100 Message-Id: <20190703155244.28166-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190703155244.28166-1-alex.bennee@linaro.org> References: <20190703155244.28166-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v1 2/4] target/arm: handle A-profile T32 semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée --- target/arm/translate.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index aaab043636..8e2e955cbe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10995,6 +10995,24 @@ static inline void gen_thumb_bkpt(DisasContext *s, int imm8) gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true)); } +/* + * Thumb SWI. On A-profile CPUs this may be a semihosting call. + */ +static inline void gen_thumb_swi(DisasContext *s, int imm8) +{ + if (semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + s->current_el != 0 && +#endif + (imm8 == 0xab)) { + gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + return; + } + gen_set_pc_im(s, s->pc); + s->svc_imm = imm8; + s->base.is_jmp = DISAS_SWI; +} + static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rn, rd, shift, cond; @@ -11752,10 +11770,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto undef; if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->pc); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; + /* swi/svc */ + gen_thumb_swi(s, extract32(insn, 0, 8)); break; } /* generate a conditional jump to next instruction */ -- 2.20.1