From: Eduardo Habkost <ehabkost@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
qemu-devel@nongnu.org,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PULL v4 37/43] i386: Replace -noTSX, -IBRS, -IBPB CPU models with aliases
Date: Wed, 3 Jul 2019 15:07:20 -0300 [thread overview]
Message-ID: <20190703180726.31267-38-ehabkost@redhat.com> (raw)
In-Reply-To: <20190703180726.31267-1-ehabkost@redhat.com>
The old CPU models will be just aliases for specific versions of
the original CPU models.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190628002844.24894-7-ehabkost@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.c | 601 ++--------------------------------------------
1 file changed, 21 insertions(+), 580 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 99ab6104f4..4646b0dde9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1439,6 +1439,7 @@ typedef struct PropValue {
typedef struct X86CPUVersionDefinition {
X86CPUVersion version;
+ const char *alias;
PropValue *props;
} X86CPUVersionDefinition;
@@ -1855,7 +1856,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Nehalem-IBRS */
+ .alias = "Nehalem-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -1866,36 +1867,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Nehalem-IBRS",
- .level = 11,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 26,
- .stepping = 3,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .xlevel = 0x80000008,
- .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Westmere",
.level = 11,
@@ -1925,7 +1896,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Westmere-IBRS */
+ .alias = "Westmere-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -1936,39 +1907,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Westmere-IBRS",
- .level = 11,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 44,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "SandyBridge",
.level = 0xd,
@@ -2003,7 +1941,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to SandyBridge-IBRS */
+ .alias = "SandyBridge-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2014,44 +1952,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "SandyBridge-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 42,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
- CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "IvyBridge",
.level = 0xd,
@@ -2089,7 +1989,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to IvyBridge-IBRS */
+ .alias = "IvyBridge-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2100,131 +2000,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "IvyBridge-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 58,
- .stepping = 9,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
- CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
- CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_ERMS,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Haswell-noTSX",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, no TSX)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Haswell-noTSX-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 1,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Haswell",
.level = 0xd,
@@ -2265,7 +2040,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Haswell-noTSX */
+ .alias = "Haswell-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2276,7 +2051,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- /* Equivalent to Haswell-IBRS */
+ .alias = "Haswell-IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2294,7 +2069,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- /* Equivalent to Haswell-noTSX-IBRS */
+ .alias = "Haswell-noTSX-IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2308,138 +2083,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Haswell-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 60,
- .stepping = 4,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Haswell, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Broadwell-noTSX",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, no TSX)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
- {
- .name = "Broadwell-noTSX-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Broadwell",
.level = 0xd,
@@ -2481,7 +2124,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Broadwell-noTSX */
+ .alias = "Broadwell-noTSX",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2491,7 +2134,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 3,
- /* Equivalent to Broadwell-IBRS */
+ .alias = "Broadwell-IBRS",
.props = (PropValue[]) {
/* Restore TSX features removed by -v2 above */
{ "hle", "on" },
@@ -2504,7 +2147,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
},
{
.version = 4,
- /* Equivalent to Broadwell-noTSX-IBRS */
+ .alias = "Broadwell-noTSX-IBRS",
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
@@ -2517,51 +2160,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Broadwell-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 61,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Broadwell, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Skylake-Client",
.level = 0xd,
@@ -2610,7 +2208,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Skylake-Client-IBRS */
+ .alias = "Skylake-Client-IBRS",
.props = (PropValue[]) {
{ "spec-ctrl", "on" },
{ "model-id",
@@ -2621,58 +2219,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Skylake-Client-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 94,
- .stepping = 3,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Core Processor (Skylake, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Skylake-Server",
.level = 0xd,
@@ -2726,7 +2272,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to Skylake-Server-IBRS */
+ .alias = "Skylake-Server-IBRS",
.props = (PropValue[]) {
/* clflushopt was not added to Skylake-Server-IBRS */
/* TODO: add -v3 including clflushopt */
@@ -2740,63 +2286,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "Skylake-Server-IBRS",
- .level = 0xd,
- .vendor = CPUID_VENDOR_INTEL,
- .family = 6,
- .model = 85,
- .stepping = 4,
- .features[FEAT_1_EDX] =
- CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
- CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
- CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
- CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
- CPUID_DE | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
- CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
- CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
- CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
- CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
- CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
- CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
- .features[FEAT_7_0_EDX] =
- CPUID_7_0_EDX_SPEC_CTRL,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
- CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
- CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
- CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
- CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
- CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
- CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
- CPUID_7_0_EBX_AVX512VL,
- .features[FEAT_7_0_ECX] =
- CPUID_7_0_ECX_PKU,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component,
- * and the only one defined in Skylake (processor tracing)
- * probably will block migration anyway.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .xlevel = 0x80000008,
- .model_id = "Intel Xeon Processor (Skylake, IBRS)",
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Cascadelake-Server",
.level = 0xd,
@@ -3258,7 +2747,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ .version = 1 },
{
.version = 2,
- /* Equivalent to EPYC-IBPB */
+ .alias = "EPYC-IBPB",
.props = (PropValue[]) {
{ "ibpb", "on" },
{ "model-id",
@@ -3269,61 +2758,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
{ /* end of list */ }
}
},
- {
- .name = "EPYC-IBPB",
- .level = 0xd,
- .vendor = CPUID_VENDOR_AMD,
- .family = 23,
- .model = 1,
- .stepping = 2,
- .features[FEAT_1_EDX] =
- CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
- CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
- CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
- CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
- CPUID_VME | CPUID_FP87,
- .features[FEAT_1_ECX] =
- CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
- CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
- CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
- CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
- CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
- .features[FEAT_8000_0001_EDX] =
- CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
- CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
- CPUID_EXT2_SYSCALL,
- .features[FEAT_8000_0001_ECX] =
- CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
- CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
- CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
- CPUID_EXT3_TOPOEXT,
- .features[FEAT_8000_0008_EBX] =
- CPUID_8000_0008_EBX_IBPB,
- .features[FEAT_7_0_EBX] =
- CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
- CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
- CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
- CPUID_7_0_EBX_SHA_NI,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component.
- */
- .features[FEAT_XSAVE] =
- CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
- .features[FEAT_6_EAX] =
- CPUID_6_EAX_ARAT,
- .features[FEAT_SVM] =
- CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
- .xlevel = 0x8000001E,
- .model_id = "AMD EPYC Processor (with IBPB)",
- .cache_info = &epyc_cache_info,
- /*
- * This CPU model will eventually be replaced by an alias,
- * don't register any versions for it.
- */
- .versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
- },
{
.name = "Dhyana",
.level = 0xd,
@@ -4648,6 +4082,13 @@ static void x86_register_cpudef_types(X86CPUDefinition *def)
name = x86_cpu_versioned_model_name(def, vdef->version);
x86_register_cpu_model_type(name, m);
g_free(name);
+
+ if (vdef->alias) {
+ X86CPUModel *am = g_new0(X86CPUModel, 1);
+ am->cpudef = def;
+ am->version = vdef->version;
+ x86_register_cpu_model_type(vdef->alias, am);
+ }
}
}
--
2.18.0.rc1.1.g3f1ff2140
next prev parent reply other threads:[~2019-07-03 18:43 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-03 18:06 [Qemu-devel] [PULL v4 00/43] Machine and x86 queue, 2019-07-03 Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 01/43] hw/boards: Add struct CpuTopology to MachineState Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 02/43] machine: Refactor smp-related call chains to pass MachineState Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 03/43] general: Replace global smp variables with smp machine properties Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 04/43] hw/ppc: Replace global smp variables with machine smp properties Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 05/43] hw/riscv: " Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 06/43] hw/s390x: " Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 07/43] hw/i386: " Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 08/43] hw/arm: " Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 09/43] hw: Replace global smp variables with MachineState for all remaining archs Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 10/43] vl.c: Replace smp global variables with smp machine properties Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 11/43] i386: Add die-level cpu topology to x86CPU on PCMachine Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 12/43] hw/i386: Adjust nr_dies with configured smp_dies for PCMachine Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 13/43] i386/cpu: Consolidate die-id validity in smp context Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 14/43] i386: Update new x86_apicid parsing rules with die_offset support Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 15/43] pc: fix possible NULL pointer dereference in pc_machine_get_device_memory_region_size() Eduardo Habkost
2019-07-03 18:06 ` [Qemu-devel] [PULL v4 16/43] machine: show if CLI option '-numa node, mem' is supported in QAPI schema Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 17/43] numa: deprecate 'mem' parameter of '-numa node' option Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 18/43] numa: deprecate implict memory distribution between nodes Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 19/43] hppa: Delete unused hppa_cpu_list() function Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 20/43] target/i386: fix feature check in hyperv-stub.c Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 21/43] deprecate -mem-path fallback to anonymous RAM Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 22/43] i386: Don't print warning if phys-bits was set automatically Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 23/43] i386: Fix signedness of hyperv_spinlock_attempts Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 24/43] i386: make 'hv-spinlocks' a regular uint32 property Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 25/43] x86/cpu: use FeatureWordArray to define filtered_features Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 26/43] i386: Remove unused host_cpudef variable Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 27/43] target/i386: Add CPUID.1F generation support for multi-dies PCMachine Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 28/43] machine: Refactor smp_parse() in vl.c as MachineClass::smp_parse() Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 29/43] vl.c: Add -smp, dies=* command line support and update doc Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 30/43] qmp: Add deprecation information to query-machines Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 31/43] i386: Introduce SnowRidge CPU model Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 32/43] qmp: Add "alias-of" field to query-cpu-definitions Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 33/43] i386: Add x-force-features option for testing Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 34/43] i386: Get model-id from CPU object on "-cpu help" Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 35/43] i386: Register versioned CPU models Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 36/43] i386: Define -IBRS, -noTSX, -IBRS versions of " Eduardo Habkost
2019-07-03 18:07 ` Eduardo Habkost [this message]
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 38/43] i386: Make unversioned CPU models be aliases Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 39/43] docs: Deprecate CPU model runnability guarantees Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 40/43] i386: Add Cascadelake-Server-v2 CPU model Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 41/43] numa: Make deprecation warnings conditional on !qtest_enabled() Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 42/43] numa: allow memory-less nodes when using memdev as backend Eduardo Habkost
2019-07-03 18:07 ` [Qemu-devel] [PULL v4 43/43] tests: use -numa memdev option in tests instead of legacy 'mem' option Eduardo Habkost
2019-07-03 18:49 ` [Qemu-devel] [PULL v4 00/43] Machine and x86 queue, 2019-07-03 Eduardo Habkost
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190703180726.31267-38-ehabkost@redhat.com \
--to=ehabkost@redhat.com \
--cc=marcel.apfelbaum@gmail.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).