From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A04AAC7618F for ; Fri, 19 Jul 2019 21:50:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EE9D21882 for ; Fri, 19 Jul 2019 21:50:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eLXlgIK5" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6EE9D21882 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hoa5M-0006kW-UP for qemu-devel@archiver.kernel.org; Fri, 19 Jul 2019 17:06:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55108) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hoa3V-0007qH-Mt for qemu-devel@nongnu.org; Fri, 19 Jul 2019 17:04:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hoa3R-0005VA-1v for qemu-devel@nongnu.org; Fri, 19 Jul 2019 17:04:40 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:39057) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hoa3H-00059d-V8 for qemu-devel@nongnu.org; Fri, 19 Jul 2019 17:04:31 -0400 Received: by mail-pg1-x542.google.com with SMTP id u17so14970014pgi.6 for ; Fri, 19 Jul 2019 14:03:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lIcDNcC73pJ/dbO0eWiulSBl7vQ6gqGkVG2Jd1sqn/E=; b=eLXlgIK54RcvRfV2MzcQp7bXLDD100NXfILyypiBC7Aee21FxnLJz6wVHdxwIbABiF TZoGx1FZqOcUUjupMx5SJNy2iH8hFZyMArBBI/MUklG94umk2p2NWDktyQcZSA+ZvUdr lMAJXi6OEPjxY2wEHKmXltiNXrBJNQZsz5drGqI5QZYViSrHJth9uP7gLbnD22Y0wyhs RqdwjEU/tzbbod1/3NlGSgnyEY0rcL3a0W3xH6YVQCEGQI/xjm2LqAylDpgVdko2VHlZ h6040nfmSReA2aJDl/+NKY0XuCKBRzdbpRXUHwIDMJwrCe1Q01aSmGwuc8yi/TRcxlkc WWog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lIcDNcC73pJ/dbO0eWiulSBl7vQ6gqGkVG2Jd1sqn/E=; b=JtGDtDnMGU7ZySSPeeVbA89i2ed4t/Uyn/6YTlhgZj7FMq7DigaC/aBi/JDbqYR78Q +JF+guhiohWUZlCMJpOiSAuNop0CVZ88o1Ov8pN4KuueIsopKOZqb+sRA3n2PbFED3v9 Yal+iAOMdUhHxfZgIw/HEBrIlPW/HV3GgKVEUNTqfrmcPdrPlYs8Ui+MH8SAJEbzRXgo HB+h5v+H8nbQk88/dHVCtotZT1xzD6FQ1jRTc9q4dZ3ViK+KS79X3keGjt+xAw4H/+12 crSUp9ZUAmxTMCSar/Fr+eh5wZd5leJZTdrbXcAIzTMUQP3hP+dsXwgUO4e7SmIM9OD/ AKyQ== X-Gm-Message-State: APjAAAVokX/EX9MxEndTglE5aVo4McooeF9Ig1/Y/0rZdwpNIHVMmckc 12KUfnpDzklUw70Tbx4mX6qDxNf/o2c= X-Google-Smtp-Source: APXvYqxGCWQAaao+DHkLvSleEZZd9+QoRSjoh8JGM6JLJEOaoYfIpmwv77b0pjkFksSdWpeOCQvANQ== X-Received: by 2002:a63:4845:: with SMTP id x5mr54694379pgk.155.1563570223446; Fri, 19 Jul 2019 14:03:43 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id i6sm32724751pgi.40.2019.07.19.14.03.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 19 Jul 2019 14:03:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 19 Jul 2019 14:03:15 -0700 Message-Id: <20190719210326.15466-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190719210326.15466-1-richard.henderson@linaro.org> References: <20190719210326.15466-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH for-4.2 13/24] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, beata.michalska@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" No functional change, but unify code sequences. Signed-off-by: Richard Henderson --- target/arm/helper.c | 118 ++++++++++++++------------------------------ 1 file changed, 37 insertions(+), 81 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9a9809ff4f..7adbf51479 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3901,70 +3901,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env, * Page D4-1736 (DDI0487A.b) */ +static int vae1_tlbmask(CPUARMState *env) +{ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + } +} + static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs = env_cpu(env); - bool sec = arm_is_secure_below_el3(env); + int mask = vae1_tlbmask(env); - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { CPUState *cs = env_cpu(env); + int mask = vae1_tlbmask(env); if (tlb_force_broadcast(env)) { tlbi_aa64_vmalle1is_write(env, NULL, value); return; } + tlb_flush_by_mmuidx(cs, mask); +} + +static int vmalle1_tlbmask(CPUARMState *env) +{ + /* + * Note that the 'ALL' scope must invalidate both stage 1 and + * stage 2 translations, whereas most other scopes only invalidate + * stage 1 translations. + */ if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); + return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + } else if (arm_feature(env, ARM_FEATURE_EL2)) { + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS; } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); + return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; } } static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); + int mask = vmalle1_tlbmask(env); - if (arm_is_secure_below_el3(env)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - if (arm_feature(env, ARM_FEATURE_EL2)) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } - } + tlb_flush_by_mmuidx(cs, mask); } static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3988,28 +3979,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ CPUState *cs = env_cpu(env); - bool sec = arm_is_secure_below_el3(env); - bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); + int mask = vmalle1_tlbmask(env); - if (sec) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else if (has_el2) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0 | - ARMMMUIdxBit_S2NS); - } else { - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); } static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4059,20 +4032,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = CPU(cpu); - bool sec = arm_is_secure_below_el3(env); + CPUState *cs = env_cpu(env); + int mask = vae1_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); - if (sec) { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask); } static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4083,8 +4047,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. */ - ARMCPU *cpu = env_archcpu(env); - CPUState *cs = CPU(cpu); + CPUState *cs = env_cpu(env); + int mask = vae1_tlbmask(env); uint64_t pageaddr = sextract64(value << 12, 0, 56); if (tlb_force_broadcast(env)) { @@ -4092,15 +4056,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } - if (arm_is_secure_below_el3(env)) { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S1SE1 | - ARMMMUIdxBit_S1SE0); - } else { - tlb_flush_page_by_mmuidx(cs, pageaddr, - ARMMMUIdxBit_S12NSE1 | - ARMMMUIdxBit_S12NSE0); - } + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); } static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, -- 2.17.1