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[97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.39 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:30 -0700 Message-Id: <20190726175032.6769-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The address of the current insn is still available in s->base.pc_next, and need not be recomputed from s->pc - 4. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0848fb933a..595385e1b1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1212,7 +1212,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1231,7 +1231,7 @@ static inline void gen_smc(DisasContext *s) */ TCGv_i32 tmp; - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tmp = tcg_const_i32(syn_aa32_smc()); gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -3190,7 +3190,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tcg_reg = load_reg(s, rn); tcg_tgtmode = tcg_const_i32(tgtmode); tcg_regno = tcg_const_i32(regno); @@ -3212,7 +3212,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tcg_reg = tcg_temp_new_i32(); tcg_tgtmode = tcg_const_i32(tgtmode); tcg_regno = tcg_const_i32(regno); @@ -7219,7 +7219,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome); tcg_isread = tcg_const_i32(isread); @@ -7629,7 +7629,7 @@ static void gen_srs(DisasContext *s, tmp = tcg_const_i32(mode); /* get_r13_banked() will raise an exception if called from System mode */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); gen_helper_get_r13_banked(addr, cpu_env, tmp); tcg_temp_free_i32(tmp); switch (amode) { -- 2.17.1