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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id g4sm84054164pfo.93.2019.07.31.13.38.14 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 31 Jul 2019 13:38:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Jul 2019 13:37:41 -0700 Message-Id: <20190731203813.30765-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH v2 00/32] target/arm: Implement ARMv8.1-VHE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" About half of this patch set is cleanup of the qemu tlb handling leading up to the actual implementation of VHE, and the biggest piece of that: The EL2&0 translation regime. Changes since v1: * Merge feedback from AJB. * Split out 7 renaming patches from "Reorganize ARMMMUIdx". * Alex's MIDR patch keeps the nested KVM from spitting warnings. I have tested qemu-system-aarch64 -accel kvm -cpu host -M virt,gic-version-host \ -m 512 -bios /usr/share/edk2/aarch64/QEMU_EFI.fd -nographic with fedora 30 system qemu, itself booted with ../bld/aarch64-softmmu/qemu-system-aarch64 \ -cpu max -M virt,gic-version=3,virtualization=on \ -drive if=virtio,file=./f30.q,format=qcow2 \ -m 4G -nographic It took a while, but eventually the nested bios arrived at the pxe boot sequence. Thankfully (?), the f30 shipped bios has debug enabled, so there's some sense of progress in the meantime. r~ Alex Bennée (2): target/arm: check TGE and E2H flags for EL0 pauth traps target/arm: generate a custom MIDR for -cpu max Richard Henderson (30): cputlb: Add tlb_set_asid_for_mmuidx cputlb: Add tlb_flush_asid_by_mmuidx and friends target/arm: Install ASIDs for long-form from EL1 target/arm: Install ASIDs for short-form from EL1 target/arm: Install ASIDs for EL2 target/arm: Define isar_feature_aa64_vh target/arm: Enable HCR_E2H for VHE target/arm: Add CONTEXTIDR_EL2 target/arm: Add TTBR1_EL2 target/arm: Update CNTVCT_EL0 for VHE target/arm: Add the hypervisor virtual counter target/arm: Add VHE system register redirection and aliasing target/arm: Split out vae1_tlbmask, vmalle1_tlbmask target/arm: Simplify tlb_force_broadcast alternatives target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 target/arm: Reorganize ARMMMUIdx target/arm: Add regime_has_2_ranges target/arm: Update arm_mmu_idx for VHE target/arm: Update arm_sctlr for VHE target/arm: Install asids for E2&0 translation regime target/arm: Flush tlbs for E2&0 translation regime target/arm: Update arm_phys_excp_target_el for TGE target/arm: Update regime_is_user for EL2&0 target/arm: Update {fp,sve}_exception_el for VHE target/arm: Enable ARMv8.1-VHE in -cpu max include/exec/cpu-all.h | 11 + include/exec/cpu-defs.h | 2 + include/exec/exec-all.h | 35 ++ include/qom/cpu.h | 2 + target/arm/cpu-qom.h | 1 + target/arm/cpu.h | 260 +++++----- target/arm/internals.h | 62 ++- target/arm/translate.h | 2 +- accel/tcg/cputlb.c | 81 +++ target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 2 + target/arm/cpu64.c | 20 + target/arm/debug_helper.c | 50 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 983 ++++++++++++++++++++++++++----------- target/arm/m_helper.c | 6 +- target/arm/pauth_helper.c | 13 +- target/arm/translate-a64.c | 13 +- target/arm/translate.c | 17 +- 19 files changed, 1088 insertions(+), 476 deletions(-) -- 2.17.1