From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH v2 13/32] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask
Date: Wed, 31 Jul 2019 13:37:54 -0700 [thread overview]
Message-ID: <20190731203813.30765-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org>
No functional change, but unify code sequences.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 118 ++++++++++++++------------------------------
1 file changed, 37 insertions(+), 81 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e9f4cae5e8..7ecaacb276 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3898,70 +3898,61 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
* Page D4-1736 (DDI0487A.b)
*/
+static int vae1_tlbmask(CPUARMState *env)
+{
+ if (arm_is_secure_below_el3(env)) {
+ return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ } else {
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
+ }
+}
+
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
- bool sec = arm_is_secure_below_el3(env);
+ int mask = vae1_tlbmask(env);
- if (sec) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
+ int mask = vae1_tlbmask(env);
if (tlb_force_broadcast(env)) {
tlbi_aa64_vmalle1is_write(env, NULL, value);
return;
}
+ tlb_flush_by_mmuidx(cs, mask);
+}
+
+static int vmalle1_tlbmask(CPUARMState *env)
+{
+ /*
+ * Note that the 'ALL' scope must invalidate both stage 1 and
+ * stage 2 translations, whereas most other scopes only invalidate
+ * stage 1 translations.
+ */
if (arm_is_secure_below_el3(env)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
+ return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ } else if (arm_feature(env, ARM_FEATURE_EL2)) {
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0 | ARMMMUIdxBit_S2NS;
} else {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
+ return ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0;
}
}
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- /* Note that the 'ALL' scope must invalidate both stage 1 and
- * stage 2 translations, whereas most other scopes only invalidate
- * stage 1 translations.
- */
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vmalle1_tlbmask(env);
- if (arm_is_secure_below_el3(env)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- if (arm_feature(env, ARM_FEATURE_EL2)) {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- } else {
- tlb_flush_by_mmuidx(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
- }
+ tlb_flush_by_mmuidx(cs, mask);
}
static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3985,28 +3976,10 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- /* Note that the 'ALL' scope must invalidate both stage 1 and
- * stage 2 translations, whereas most other scopes only invalidate
- * stage 1 translations.
- */
CPUState *cs = env_cpu(env);
- bool sec = arm_is_secure_below_el3(env);
- bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
+ int mask = vmalle1_tlbmask(env);
- if (sec) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else if (has_el2) {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0 |
- ARMMMUIdxBit_S2NS);
- } else {
- tlb_flush_by_mmuidx_all_cpus_synced(cs,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, mask);
}
static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4056,20 +4029,11 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
- bool sec = arm_is_secure_below_el3(env);
+ CPUState *cs = env_cpu(env);
+ int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- if (sec) {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, mask);
}
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4080,8 +4044,8 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
* since we don't support flush-for-specific-ASID-only or
* flush-last-level-only.
*/
- ARMCPU *cpu = env_archcpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
+ int mask = vae1_tlbmask(env);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (tlb_force_broadcast(env)) {
@@ -4089,15 +4053,7 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
return;
}
- if (arm_is_secure_below_el3(env)) {
- tlb_flush_page_by_mmuidx(cs, pageaddr,
- ARMMMUIdxBit_S1SE1 |
- ARMMMUIdxBit_S1SE0);
- } else {
- tlb_flush_page_by_mmuidx(cs, pageaddr,
- ARMMMUIdxBit_S12NSE1 |
- ARMMMUIdxBit_S12NSE0);
- }
+ tlb_flush_page_by_mmuidx(cs, pageaddr, mask);
}
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
--
2.17.1
next prev parent reply other threads:[~2019-07-31 20:46 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 20:37 [Qemu-devel] [PATCH v2 00/32] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 01/32] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 02/32] cputlb: Add tlb_flush_asid_by_mmuidx and friends Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 03/32] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 04/32] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 05/32] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 06/32] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 07/32] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 08/32] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 09/32] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 10/32] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 11/32] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 12/32] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-31 20:37 ` Richard Henderson [this message]
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 14/32] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 15/32] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 17/32] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 18/32] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 19/32] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 20/32] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 21/32] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 22/32] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 24/32] target/arm: Update arm_sctlr " Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 25/32] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 26/32] target/arm: Flush tlbs " Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 27/32] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 28/32] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 29/32] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 30/32] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 31/32] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 32/32] target/arm: generate a custom MIDR for -cpu max Richard Henderson
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