From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH v2 18/32] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE*
Date: Wed, 31 Jul 2019 13:37:59 -0700 [thread overview]
Message-ID: <20190731203813.30765-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
The Secure regimes all have a single stage translation;
there is no point in pointing out that the idx is for stage1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 8 ++++----
target/arm/internals.h | 4 ++--
target/arm/translate.h | 2 +-
target/arm/helper.c | 30 +++++++++++++++---------------
target/arm/translate-a64.c | 4 ++--
target/arm/translate.c | 6 +++---
6 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index ade558f63c..c7ce8a4da5 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2854,8 +2854,8 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_S1E3 = 3 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1SE0 = 4 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1SE1 = 5 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A,
+ ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A,
ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_A,
ARMMMUIdx_MUser = 0 | ARM_MMU_IDX_M,
ARMMMUIdx_MPriv = 1 | ARM_MMU_IDX_M,
@@ -2880,8 +2880,8 @@ typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_EL10_1 = 1 << 1,
ARMMMUIdxBit_S1E2 = 1 << 2,
ARMMMUIdxBit_S1E3 = 1 << 3,
- ARMMMUIdxBit_S1SE0 = 1 << 4,
- ARMMMUIdxBit_S1SE1 = 1 << 5,
+ ARMMMUIdxBit_SE0 = 1 << 4,
+ ARMMMUIdxBit_SE1 = 1 << 5,
ARMMMUIdxBit_Stage2 = 1 << 6,
ARMMMUIdxBit_MUser = 1 << 0,
ARMMMUIdxBit_MPriv = 1 << 1,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index cd9b1acb20..c505cae30c 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -820,8 +820,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_MUser:
return false;
case ARMMMUIdx_S1E3:
- case ARMMMUIdx_S1SE0:
- case ARMMMUIdx_S1SE1:
+ case ARMMMUIdx_SE0:
+ case ARMMMUIdx_SE1:
case ARMMMUIdx_MSPrivNegPri:
case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPriv:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index a20f6e2056..715fa08e3b 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -122,7 +122,7 @@ static inline int default_exception_el(DisasContext *s)
* exceptions can only be routed to ELs above 1, so we target the higher of
* 1 or the current EL.
*/
- return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
+ return (s->mmu_idx == ARMMMUIdx_SE0 && s->secure_routed_to_el3)
? 3 : MAX(1, s->current_el);
}
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4c0c314c1a..e0d4f33026 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -566,7 +566,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
switch (ri->secure) {
case ARM_CP_SECSTATE_S:
- idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ idxmask = ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
break;
case ARM_CP_SECSTATE_NS:
idxmask = ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
@@ -3122,7 +3122,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
mmu_idx = ARMMMUIdx_Stage1_E1;
break;
case 1:
- mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
+ mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
break;
default:
g_assert_not_reached();
@@ -3132,13 +3132,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
switch (el) {
case 3:
- mmu_idx = ARMMMUIdx_S1SE0;
+ mmu_idx = ARMMMUIdx_SE0;
break;
case 2:
mmu_idx = ARMMMUIdx_Stage1_E0;
break;
case 1:
- mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
+ mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0;
break;
default:
g_assert_not_reached();
@@ -3192,7 +3192,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
case 0:
switch (ri->opc1) {
case 0: /* AT S1E1R, AT S1E1W */
- mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1;
+ mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
break;
case 4: /* AT S1E2R, AT S1E2W */
mmu_idx = ARMMMUIdx_S1E2;
@@ -3205,13 +3205,13 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
}
break;
case 2: /* AT S1E0R, AT S1E0W */
- mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0;
+ mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_Stage1_E0;
break;
case 4: /* AT S12E1R, AT S12E1W */
- mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_EL10_1;
+ mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_EL10_1;
break;
case 6: /* AT S12E0R, AT S12E0W */
- mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_EL10_0;
+ mmu_idx = secure ? ARMMMUIdx_SE0 : ARMMMUIdx_EL10_0;
break;
default:
g_assert_not_reached();
@@ -3424,7 +3424,7 @@ static void update_lpae_el1_asid(CPUARMState *env, int secure)
ttcr = env->cp15.tcr_el[3].raw_tcr;
/* Note that cp15.ttbr0_s == cp15.ttbr0_el[3], so S1E3 is affected. */
/* ??? Secure EL3 really using the ASID field? Doesn't make sense. */
- idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0 | ARMMMUIdxBit_S1E3;
+ idxmask = ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0 | ARMMMUIdxBit_S1E3;
break;
case ARM_CP_SECSTATE_NS:
ttbr0 = env->cp15.ttbr0_ns;
@@ -3899,7 +3899,7 @@ static CPAccessResult aa64_cacheop_access(CPUARMState *env,
static int vae1_tlbmask(CPUARMState *env)
{
if (arm_is_secure_below_el3(env)) {
- return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
} else {
return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0;
}
@@ -3935,7 +3935,7 @@ static int vmalle1_tlbmask(CPUARMState *env)
* stage 1 translations.
*/
if (arm_is_secure_below_el3(env)) {
- return ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0;
+ return ARMMMUIdxBit_SE1 | ARMMMUIdxBit_SE0;
} else if (arm_feature(env, ARM_FEATURE_EL2)) {
return ARMMMUIdxBit_EL10_1 | ARMMMUIdxBit_EL10_0 | ARMMMUIdxBit_Stage2;
} else {
@@ -8695,9 +8695,9 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
return 2;
case ARMMMUIdx_S1E3:
return 3;
- case ARMMMUIdx_S1SE0:
+ case ARMMMUIdx_SE0:
return arm_el_is_aa64(env, 3) ? 1 : 3;
- case ARMMMUIdx_S1SE1:
+ case ARMMMUIdx_SE1:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
case ARMMMUIdx_MPrivNegPri:
@@ -8836,7 +8836,7 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
- case ARMMMUIdx_S1SE0:
+ case ARMMMUIdx_SE0:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
case ARMMMUIdx_MSUser:
@@ -11279,7 +11279,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env)
el = arm_current_el(env);
if (el < 2 && arm_is_secure_below_el3(env)) {
- return ARMMMUIdx_S1SE0 + el;
+ return ARMMMUIdx_SE0 + el;
} else {
return ARMMMUIdx_EL10_0 + el;
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 73801c5df7..dbe2189e51 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -116,8 +116,8 @@ static inline int get_a64_user_mem_index(DisasContext *s)
case ARMMMUIdx_EL10_1:
useridx = ARMMMUIdx_EL10_0;
break;
- case ARMMMUIdx_S1SE1:
- useridx = ARMMMUIdx_S1SE0;
+ case ARMMMUIdx_SE1:
+ useridx = ARMMMUIdx_SE0;
break;
case ARMMMUIdx_Stage2:
g_assert_not_reached();
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 995010834f..1fc2bf8a52 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -157,9 +157,9 @@ static inline int get_a32_user_mem_index(DisasContext *s)
case ARMMMUIdx_EL10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
case ARMMMUIdx_S1E3:
- case ARMMMUIdx_S1SE0:
- case ARMMMUIdx_S1SE1:
- return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0);
+ case ARMMMUIdx_SE0:
+ case ARMMMUIdx_SE1:
+ return arm_to_core_mmu_idx(ARMMMUIdx_SE0);
case ARMMMUIdx_MUser:
case ARMMMUIdx_MPriv:
return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
--
2.17.1
next prev parent reply other threads:[~2019-07-31 20:47 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 20:37 [Qemu-devel] [PATCH v2 00/32] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 01/32] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 02/32] cputlb: Add tlb_flush_asid_by_mmuidx and friends Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 03/32] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 04/32] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 05/32] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 06/32] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 07/32] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 08/32] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 09/32] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 10/32] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 11/32] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 12/32] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 13/32] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 14/32] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 15/32] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 17/32] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2019-07-31 20:37 ` Richard Henderson [this message]
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 19/32] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 20/32] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 21/32] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 22/32] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 24/32] target/arm: Update arm_sctlr " Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 25/32] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 26/32] target/arm: Flush tlbs " Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 27/32] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 28/32] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 29/32] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 30/32] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 31/32] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 32/32] target/arm: generate a custom MIDR for -cpu max Richard Henderson
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