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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id g4sm84054164pfo.93.2019.07.31.13.38.15 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Wed, 31 Jul 2019 13:38:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 31 Jul 2019 13:37:42 -0700 Message-Id: <20190731203813.30765-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org> References: <20190731203813.30765-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 01/32] cputlb: Add tlb_set_asid_for_mmuidx X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Although we can't do much with ASIDs except remember them, this will allow cleanups within target/ that should make things clearer. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v2: Assert cpu_is_self; only flush idx w/ asid mismatch. v3: Improve asid comment. --- include/exec/cpu-all.h | 11 +++++++++++ include/exec/cpu-defs.h | 2 ++ include/exec/exec-all.h | 19 +++++++++++++++++++ accel/tcg/cputlb.c | 26 ++++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 536ea58f81..40b140cbba 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -439,4 +439,15 @@ static inline CPUTLB *env_tlb(CPUArchState *env) return &env_neg(env)->tlb; } +/** + * cpu_tlb(env) + * @cpu: The generic CPUState + * + * Return the CPUTLB state associated with the cpu. + */ +static inline CPUTLB *cpu_tlb(CPUState *cpu) +{ + return &cpu_neg(cpu)->tlb; +} + #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 9bc713a70b..b42986d822 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -169,6 +169,8 @@ typedef struct CPUTLBDesc { size_t n_used_entries; /* The next index to use in the tlb victim table. */ size_t vindex; + /* The current ASID for this tlb, if used; otherwise ignored. */ + uint32_t asid; /* The tlb victim table, in two parts. */ CPUTLBEntry vtable[CPU_VTLB_SIZE]; CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 16034ee651..9c77aa5bf9 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -225,6 +225,21 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); * depend on when the guests translation ends the TB. */ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); +/** + * tlb_set_asid_for_mmuidx: + * @cpu: Originating cpu + * @asid: Address Space Identifier + * @idxmap: bitmap of MMU indexes to set to @asid + * @depmap: bitmap of dependent MMU indexes + * + * Set an ASID for all of @idxmap. If any previous ASID was different, + * then we will flush the mmu idx. If a flush is required, then also flush + * all dependent mmu indicies in @depmap. This latter is typically used + * for secondary page resolution, for implementing virtualization within + * the guest. + */ +void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, + uint16_t idxmap, uint16_t dep_idxmap); /** * tlb_set_page_with_attrs: * @cpu: CPU to add this TLB entry for @@ -310,6 +325,10 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap) { } +static inline void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, + uint16_t idxmap, uint16_t depmap) +{ +} #endif #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index bb9897b25a..c68f57755b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -540,6 +540,32 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } +void tlb_set_asid_for_mmuidx(CPUState *cpu, uint32_t asid, uint16_t idxmap, + uint16_t depmap) +{ + CPUTLB *tlb = cpu_tlb(cpu); + uint16_t work, to_flush = 0; + + /* It doesn't make sense to set context across cpus. */ + assert_cpu_is_self(cpu); + + /* + * We don't support ASIDs except for trivially. + * If there is any change, then we must flush the TLB. + */ + for (work = idxmap; work != 0; work &= work - 1) { + int mmu_idx = ctz32(work); + if (tlb->d[mmu_idx].asid != asid) { + tlb->d[mmu_idx].asid = asid; + to_flush |= 1 << mmu_idx; + } + } + if (to_flush) { + to_flush |= depmap; + tlb_flush_by_mmuidx_async_work(cpu, RUN_ON_CPU_HOST_INT(to_flush)); + } +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) -- 2.17.1