From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org
Subject: [Qemu-devel] [PATCH v2 20/32] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2
Date: Wed, 31 Jul 2019 13:38:01 -0700 [thread overview]
Message-ID: <20190731203813.30765-21-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190731203813.30765-1-richard.henderson@linaro.org>
This is part of a reorganization to the set of mmu_idx.
The non-secure EL2 regime only has a single stage translation;
there is no point in pointing out that the idx is for stage1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/internals.h | 2 +-
target/arm/helper.c | 24 ++++++++++++------------
target/arm/translate.c | 2 +-
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 94337b2fb0..552269daad 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2852,7 +2852,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
typedef enum ARMMMUIdx {
ARMMMUIdx_EL10_0 = 0 | ARM_MMU_IDX_A,
ARMMMUIdx_EL10_1 = 1 | ARM_MMU_IDX_A,
- ARMMMUIdx_S1E2 = 2 | ARM_MMU_IDX_A,
+ ARMMMUIdx_E2 = 2 | ARM_MMU_IDX_A,
ARMMMUIdx_SE3 = 3 | ARM_MMU_IDX_A,
ARMMMUIdx_SE0 = 4 | ARM_MMU_IDX_A,
ARMMMUIdx_SE1 = 5 | ARM_MMU_IDX_A,
@@ -2878,7 +2878,7 @@ typedef enum ARMMMUIdx {
typedef enum ARMMMUIdxBit {
ARMMMUIdxBit_EL10_0 = 1 << 0,
ARMMMUIdxBit_EL10_1 = 1 << 1,
- ARMMMUIdxBit_S1E2 = 1 << 2,
+ ARMMMUIdxBit_E2 = 1 << 2,
ARMMMUIdxBit_SE3 = 1 << 3,
ARMMMUIdxBit_SE0 = 1 << 4,
ARMMMUIdxBit_SE1 = 1 << 5,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index dbb46da549..027878516f 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -812,7 +812,7 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
case ARMMMUIdx_EL10_1:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_Stage1_E1:
- case ARMMMUIdx_S1E2:
+ case ARMMMUIdx_E2:
case ARMMMUIdx_Stage2:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e5b07b4770..69c913d824 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -740,7 +740,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
CPUState *cs = env_cpu(env);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
}
static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -748,7 +748,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
CPUState *cs = env_cpu(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
}
static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -757,7 +757,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = env_cpu(env);
uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
}
static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -767,7 +767,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1E2);
+ ARMMMUIdxBit_E2);
}
static const ARMCPRegInfo cp_reginfo[] = {
@@ -3167,7 +3167,7 @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
uint64_t par64;
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S1E2);
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
@@ -3195,7 +3195,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
mmu_idx = secure ? ARMMMUIdx_SE1 : ARMMMUIdx_Stage1_E1;
break;
case 4: /* AT S1E2R, AT S1E2W */
- mmu_idx = ARMMMUIdx_S1E2;
+ mmu_idx = ARMMMUIdx_E2;
break;
case 6: /* AT S1E3R, AT S1E3W */
mmu_idx = ARMMMUIdx_SE3;
@@ -3958,7 +3958,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu);
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2);
}
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -3984,7 +3984,7 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
CPUState *cs = env_cpu(env);
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_S1E2);
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2);
}
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4006,7 +4006,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56);
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_S1E2);
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2);
}
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4059,7 +4059,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr,
- ARMMMUIdxBit_S1E2);
+ ARMMMUIdxBit_E2);
}
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4375,7 +4375,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
.access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
- /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
+ /* AT E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
{ .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
.access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
@@ -8691,7 +8691,7 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
case ARMMMUIdx_Stage2:
- case ARMMMUIdx_S1E2:
+ case ARMMMUIdx_E2:
return 2;
case ARMMMUIdx_SE3:
return 3;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5372947e47..4e79dbbdfc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -152,7 +152,7 @@ static inline int get_a32_user_mem_index(DisasContext *s)
* otherwise, access as if at PL0.
*/
switch (s->mmu_idx) {
- case ARMMMUIdx_S1E2: /* this one is UNPREDICTABLE */
+ case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */
case ARMMMUIdx_EL10_0:
case ARMMMUIdx_EL10_1:
return arm_to_core_mmu_idx(ARMMMUIdx_EL10_0);
--
2.17.1
next prev parent reply other threads:[~2019-07-31 20:47 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 20:37 [Qemu-devel] [PATCH v2 00/32] target/arm: Implement ARMv8.1-VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 01/32] cputlb: Add tlb_set_asid_for_mmuidx Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 02/32] cputlb: Add tlb_flush_asid_by_mmuidx and friends Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 03/32] target/arm: Install ASIDs for long-form from EL1 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 04/32] target/arm: Install ASIDs for short-form " Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 05/32] target/arm: Install ASIDs for EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 06/32] target/arm: Define isar_feature_aa64_vh Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 07/32] target/arm: Enable HCR_E2H for VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 08/32] target/arm: Add CONTEXTIDR_EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 09/32] target/arm: Add TTBR1_EL2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 10/32] target/arm: Update CNTVCT_EL0 for VHE Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 11/32] target/arm: Add the hypervisor virtual counter Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 12/32] target/arm: Add VHE system register redirection and aliasing Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 13/32] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 14/32] target/arm: Simplify tlb_force_broadcast alternatives Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 15/32] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_* Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 16/32] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 17/32] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Richard Henderson
2019-07-31 20:37 ` [Qemu-devel] [PATCH v2 18/32] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE* Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 19/32] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 Richard Henderson
2019-07-31 20:38 ` Richard Henderson [this message]
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 21/32] target/arm: Reorganize ARMMMUIdx Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 22/32] target/arm: Add regime_has_2_ranges Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 23/32] target/arm: Update arm_mmu_idx for VHE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 24/32] target/arm: Update arm_sctlr " Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 25/32] target/arm: Install asids for E2&0 translation regime Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 26/32] target/arm: Flush tlbs " Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 27/32] target/arm: Update arm_phys_excp_target_el for TGE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 28/32] target/arm: Update regime_is_user for EL2&0 Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 29/32] target/arm: Update {fp, sve}_exception_el for VHE Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 30/32] target/arm: Enable ARMv8.1-VHE in -cpu max Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 31/32] target/arm: check TGE and E2H flags for EL0 pauth traps Richard Henderson
2019-07-31 20:38 ` [Qemu-devel] [PATCH v2 32/32] target/arm: generate a custom MIDR for -cpu max Richard Henderson
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