From: Jan Bobek <jan.bobek@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Jan Bobek" <jan.bobek@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [Qemu-devel] [RFC PATCH v2 33/39] target/i386: introduce MMX instructions to insn.h
Date: Sat, 10 Aug 2019 00:12:49 -0400 [thread overview]
Message-ID: <20190810041255.6820-34-jan.bobek@gmail.com> (raw)
In-Reply-To: <20190810041255.6820-1-jan.bobek@gmail.com>
Add all MMX instruction entries to insn.h.
Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
target/i386/insn.h | 131 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/target/i386/insn.h b/target/i386/insn.h
index 4b48c0c0e1..6506ff3137 100644
--- a/target/i386/insn.h
+++ b/target/i386/insn.h
@@ -66,6 +66,137 @@
# define INSN_GRP_END(grpname)
#endif /* INSN_GRP_END */
+/* NP 0F 6E /r: MOVD mm,r/m32 */
+INSN_WR(movd, LEG(NP, 0F, 0), 0x6e, MMX, Pq, Ed)
+/* NP 0F 7E /r: MOVD r/m32,mm */
+INSN_WR(movd, LEG(NP, 0F, 0), 0x7e, MMX, Ed, Pq)
+/* NP REX.W + 0F 6E /r: MOVQ mm,r/m64 */
+INSN_WR(movq, LEG(NP, 0F, 1), 0x6e, MMX, Pq, Eq)
+/* NP REX.W + 0F 7E /r: MOVQ r/m64,mm */
+INSN_WR(movq, LEG(NP, 0F, 1), 0x7e, MMX, Eq, Pq)
+/* NP 0F 6F /r: MOVQ mm, mm/m64 */
+INSN_WR(movq, LEG(NP, 0F, 0), 0x6f, MMX, Pq, Qq)
+/* NP 0F 7F /r: MOVQ mm/m64, mm */
+INSN_WR(movq, LEG(NP, 0F, 0), 0x7f, MMX, Qq, Pq)
+/* NP 0F FC /r: PADDB mm, mm/m64 */
+INSN_WRR(paddb, LEG(NP, 0F, 0), 0xfc, MMX, Pq, Pq, Qq)
+/* NP 0F FD /r: PADDW mm, mm/m64 */
+INSN_WRR(paddw, LEG(NP, 0F, 0), 0xfd, MMX, Pq, Pq, Qq)
+/* NP 0F FE /r: PADDD mm, mm/m64 */
+INSN_WRR(paddd, LEG(NP, 0F, 0), 0xfe, MMX, Pq, Pq, Qq)
+/* NP 0F EC /r: PADDSB mm, mm/m64 */
+INSN_WRR(paddsb, LEG(NP, 0F, 0), 0xec, MMX, Pq, Pq, Qq)
+/* NP 0F ED /r: PADDSW mm, mm/m64 */
+INSN_WRR(paddsw, LEG(NP, 0F, 0), 0xed, MMX, Pq, Pq, Qq)
+/* NP 0F DC /r: PADDUSB mm,mm/m64 */
+INSN_WRR(paddusb, LEG(NP, 0F, 0), 0xdc, MMX, Pq, Pq, Qq)
+/* NP 0F DD /r: PADDUSW mm,mm/m64 */
+INSN_WRR(paddusw, LEG(NP, 0F, 0), 0xdd, MMX, Pq, Pq, Qq)
+/* NP 0F F8 /r: PSUBB mm, mm/m64 */
+INSN_WRR(psubb, LEG(NP, 0F, 0), 0xf8, MMX, Pq, Pq, Qq)
+/* NP 0F F9 /r: PSUBW mm, mm/m64 */
+INSN_WRR(psubw, LEG(NP, 0F, 0), 0xf9, MMX, Pq, Pq, Qq)
+/* NP 0F FA /r: PSUBD mm, mm/m64 */
+INSN_WRR(psubd, LEG(NP, 0F, 0), 0xfa, MMX, Pq, Pq, Qq)
+/* NP 0F E8 /r: PSUBSB mm, mm/m64 */
+INSN_WRR(psubsb, LEG(NP, 0F, 0), 0xe8, MMX, Pq, Pq, Qq)
+/* NP 0F E9 /r: PSUBSW mm, mm/m64 */
+INSN_WRR(psubsw, LEG(NP, 0F, 0), 0xe9, MMX, Pq, Pq, Qq)
+/* NP 0F D8 /r: PSUBUSB mm, mm/m64 */
+INSN_WRR(psubusb, LEG(NP, 0F, 0), 0xd8, MMX, Pq, Pq, Qq)
+/* NP 0F D9 /r: PSUBUSW mm, mm/m64 */
+INSN_WRR(psubusw, LEG(NP, 0F, 0), 0xd9, MMX, Pq, Pq, Qq)
+/* NP 0F D5 /r: PMULLW mm, mm/m64 */
+INSN_WRR(pmullw, LEG(NP, 0F, 0), 0xd5, MMX, Pq, Pq, Qq)
+/* NP 0F E5 /r: PMULHW mm, mm/m64 */
+INSN_WRR(pmulhw, LEG(NP, 0F, 0), 0xe5, MMX, Pq, Pq, Qq)
+/* NP 0F F5 /r: PMADDWD mm, mm/m64 */
+INSN_WRR(pmaddwd, LEG(NP, 0F, 0), 0xf5, MMX, Pq, Pq, Qq)
+/* NP 0F 74 /r: PCMPEQB mm,mm/m64 */
+INSN_WRR(pcmpeqb, LEG(NP, 0F, 0), 0x74, MMX, Pq, Pq, Qq)
+/* NP 0F 75 /r: PCMPEQW mm,mm/m64 */
+INSN_WRR(pcmpeqw, LEG(NP, 0F, 0), 0x75, MMX, Pq, Pq, Qq)
+/* NP 0F 76 /r: PCMPEQD mm,mm/m64 */
+INSN_WRR(pcmpeqd, LEG(NP, 0F, 0), 0x76, MMX, Pq, Pq, Qq)
+/* NP 0F 64 /r: PCMPGTB mm,mm/m64 */
+INSN_WRR(pcmpgtb, LEG(NP, 0F, 0), 0x64, MMX, Pq, Pq, Qq)
+/* NP 0F 65 /r: PCMPGTW mm,mm/m64 */
+INSN_WRR(pcmpgtw, LEG(NP, 0F, 0), 0x65, MMX, Pq, Pq, Qq)
+/* NP 0F 66 /r: PCMPGTD mm,mm/m64 */
+INSN_WRR(pcmpgtd, LEG(NP, 0F, 0), 0x66, MMX, Pq, Pq, Qq)
+/* NP 0F DB /r: PAND mm, mm/m64 */
+INSN_WRR(pand, LEG(NP, 0F, 0), 0xdb, MMX, Pq, Pq, Qq)
+/* NP 0F DF /r: PANDN mm, mm/m64 */
+INSN_WRR(pandn, LEG(NP, 0F, 0), 0xdf, MMX, Pq, Pq, Qq)
+/* NP 0F EB /r: POR mm, mm/m64 */
+INSN_WRR(por, LEG(NP, 0F, 0), 0xeb, MMX, Pq, Pq, Qq)
+/* NP 0F EF /r: PXOR mm, mm/m64 */
+INSN_WRR(pxor, LEG(NP, 0F, 0), 0xef, MMX, Pq, Pq, Qq)
+/* NP 0F F1 /r: PSLLW mm, mm/m64 */
+INSN_WRR(psllw, LEG(NP, 0F, 0), 0xf1, MMX, Pq, Pq, Qq)
+/* NP 0F F2 /r: PSLLD mm, mm/m64 */
+INSN_WRR(pslld, LEG(NP, 0F, 0), 0xf2, MMX, Pq, Pq, Qq)
+/* NP 0F F3 /r: PSLLQ mm, mm/m64 */
+INSN_WRR(psllq, LEG(NP, 0F, 0), 0xf3, MMX, Pq, Pq, Qq)
+/* NP 0F D1 /r: PSRLW mm, mm/m64 */
+INSN_WRR(psrlw, LEG(NP, 0F, 0), 0xd1, MMX, Pq, Pq, Qq)
+/* NP 0F D2 /r: PSRLD mm, mm/m64 */
+INSN_WRR(psrld, LEG(NP, 0F, 0), 0xd2, MMX, Pq, Pq, Qq)
+/* NP 0F D3 /r: PSRLQ mm, mm/m64 */
+INSN_WRR(psrlq, LEG(NP, 0F, 0), 0xd3, MMX, Pq, Pq, Qq)
+/* NP 0F E1 /r: PSRAW mm,mm/m64 */
+INSN_WRR(psraw, LEG(NP, 0F, 0), 0xe1, MMX, Pq, Pq, Qq)
+/* NP 0F E2 /r: PSRAD mm,mm/m64 */
+INSN_WRR(psrad, LEG(NP, 0F, 0), 0xe2, MMX, Pq, Pq, Qq)
+/* NP 0F 63 /r: PACKSSWB mm1, mm2/m64 */
+INSN_WRR(packsswb, LEG(NP, 0F, 0), 0x63, MMX, Pq, Pq, Qq)
+/* NP 0F 6B /r: PACKSSDW mm1, mm2/m64 */
+INSN_WRR(packssdw, LEG(NP, 0F, 0), 0x6b, MMX, Pq, Pq, Qq)
+/* NP 0F 67 /r: PACKUSWB mm, mm/m64 */
+INSN_WRR(packuswb, LEG(NP, 0F, 0), 0x67, MMX, Pq, Pq, Qq)
+/* NP 0F 68 /r: PUNPCKHBW mm, mm/m64 */
+INSN_WRR(punpckhbw, LEG(NP, 0F, 0), 0x68, MMX, Pq, Pq, Qq)
+/* NP 0F 69 /r: PUNPCKHWD mm, mm/m64 */
+INSN_WRR(punpckhwd, LEG(NP, 0F, 0), 0x69, MMX, Pq, Pq, Qq)
+/* NP 0F 6A /r: PUNPCKHDQ mm, mm/m64 */
+INSN_WRR(punpckhdq, LEG(NP, 0F, 0), 0x6a, MMX, Pq, Pq, Qq)
+/* NP 0F 60 /r: PUNPCKLBW mm, mm/m32 */
+INSN_WRR(punpcklbw, LEG(NP, 0F, 0), 0x60, MMX, Pq, Pq, Qd)
+/* NP 0F 61 /r: PUNPCKLWD mm, mm/m32 */
+INSN_WRR(punpcklwd, LEG(NP, 0F, 0), 0x61, MMX, Pq, Pq, Qd)
+/* NP 0F 62 /r: PUNPCKLDQ mm, mm/m32 */
+INSN_WRR(punpckldq, LEG(NP, 0F, 0), 0x62, MMX, Pq, Pq, Qd)
+/* NP 0F 77: EMMS */
+INSN(emms, LEG(NP, 0F, 0), 0x77, MMX)
+
+INSN_GRP(grp12_LEG_NP, LEG(NP, 0F, 0), 0x71)
+INSN_GRP_BEGIN(grp12_LEG_NP)
+ /* NP 0F 71 /6 ib: PSLLW mm1, imm8 */
+ INSN_GRPMEMB_WRR(grp12_LEG_NP, psllw, 6, MMX, Nq, Nq, Ib)
+ /* NP 0F 71 /2 ib: PSRLW mm, imm8 */
+ INSN_GRPMEMB_WRR(grp12_LEG_NP, psrlw, 2, MMX, Nq, Nq, Ib)
+ /* NP 0F 71 /4 ib: PSRAW mm,imm8 */
+ INSN_GRPMEMB_WRR(grp12_LEG_NP, psraw, 4, MMX, Nq, Nq, Ib)
+INSN_GRP_END(grp12_LEG_NP)
+
+INSN_GRP(grp13_LEG_NP, LEG(NP, 0F, 0), 0x72)
+INSN_GRP_BEGIN(grp13_LEG_NP)
+ /* NP 0F 72 /6 ib: PSLLD mm, imm8 */
+ INSN_GRPMEMB_WRR(grp13_LEG_NP, pslld, 6, MMX, Nq, Nq, Ib)
+ /* NP 0F 72 /2 ib: PSRLD mm, imm8 */
+ INSN_GRPMEMB_WRR(grp13_LEG_NP, psrld, 2, MMX, Nq, Nq, Ib)
+ /* NP 0F 72 /4 ib: PSRAD mm,imm8 */
+ INSN_GRPMEMB_WRR(grp13_LEG_NP, psrad, 4, MMX, Nq, Nq, Ib)
+INSN_GRP_END(grp13_LEG_NP)
+
+INSN_GRP(grp14_LEG_NP, LEG(NP, 0F, 0), 0x73)
+INSN_GRP_BEGIN(grp14_LEG_NP)
+ /* NP 0F 73 /6 ib: PSLLQ mm, imm8 */
+ INSN_GRPMEMB_WRR(grp14_LEG_NP, psllq, 6, MMX, Nq, Nq, Ib)
+ /* NP 0F 73 /2 ib: PSRLQ mm, imm8 */
+ INSN_GRPMEMB_WRR(grp14_LEG_NP, psrlq, 2, MMX, Nq, Nq, Ib)
+INSN_GRP_END(grp14_LEG_NP)
+
#undef LEG
#undef VEX
#undef INSN
--
2.20.1
next prev parent reply other threads:[~2019-08-10 4:25 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-10 4:12 [Qemu-devel] [RFC PATCH v2 00/39] rewrite MMX/SSE instruction translation Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 01/39] target/i386: Push rex_r into DisasContext Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 02/39] target/i386: Push rex_w " Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 03/39] target/i386: reduce scope of variable aflag Jan Bobek
2019-08-13 4:47 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 04/39] target/i386: use dflag from DisasContext Jan Bobek
2019-08-13 4:48 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 05/39] target/i386: use prefix " Jan Bobek
2019-08-13 4:48 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 06/39] target/i386: Simplify gen_exception arguments Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 07/39] target/i386: use pc_start from DisasContext Jan Bobek
2019-08-13 4:47 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 08/39] target/i386: make variable b1 const Jan Bobek
2019-08-13 4:49 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 09/39] target/i386: make variable is_xmm const Jan Bobek
2019-08-13 4:52 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 10/39] target/i386: add vector register file alignment constraints Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 11/39] target/i386: introduce gen_(ld, st)d_env_A0 Jan Bobek
2019-08-13 4:56 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 12/39] target/i386: introduce gen_sse_ng Jan Bobek
2019-08-13 5:00 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 13/39] target/i386: disable unused function warning temporarily Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 14/39] target/i386: introduce mnemonic aliases for several gvec operations Jan Bobek
2019-08-13 5:01 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 15/39] target/i386: introduce function ck_cpuid Jan Bobek
2019-08-13 5:07 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 16/39] target/i386: introduce instruction operand infrastructure Jan Bobek
2019-08-13 6:07 ` Richard Henderson
2019-08-15 0:00 ` Jan Bobek
2019-08-15 9:09 ` Richard Henderson
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 17/39] target/i386: introduce helpers for decoding modrm fields Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 18/39] target/i386: introduce modifier for direct-only operand decoding Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 19/39] target/i386: introduce generic operand alias Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 20/39] target/i386: introduce generic load-store operand Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 21/39] target/i386: introduce insn.h Jan Bobek
2019-08-13 6:00 ` Richard Henderson
2019-08-15 0:55 ` Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 22/39] target/i386: introduce code generators Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 23/39] target/i386: introduce instruction translator macros Jan Bobek
2019-08-13 6:30 ` Richard Henderson
2019-08-15 0:51 ` Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 24/39] target/i386: introduce Ib (immediate) operand Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 25/39] target/i386: introduce M* (memptr) operands Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 26/39] target/i386: introduce G*, R*, E* (general register) operands Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 27/39] target/i386: introduce RdMw operand Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 28/39] target/i386: introduce P*, N*, Q* (MMX) operands Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 29/39] target/i386: introduce helper-based code generator macros Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 30/39] target/i386: introduce gvec-based " Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 31/39] target/i386: introduce MMX translators Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 32/39] target/i386: introduce MMX code generators Jan Bobek
2019-08-10 4:12 ` Jan Bobek [this message]
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 34/39] target/i386: introduce V*, U*, W* (SSE/AVX) operands Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 35/39] target/i386: introduce UdqMq operand Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 36/39] target/i386: introduce SSE translators Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 37/39] target/i386: introduce SSE code generators Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 38/39] target/i386: introduce SSE instructions to insn.h Jan Bobek
2019-08-10 4:12 ` [Qemu-devel] [RFC PATCH v2 39/39] target/i386: introduce memory-pointer operand read/write workarounds Jan Bobek
2019-08-10 4:44 ` [Qemu-devel] [RFC PATCH v2 00/39] rewrite MMX/SSE instruction translation no-reply
2019-08-10 23:35 ` Richard Henderson
2019-08-11 15:49 ` Jan Bobek
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