From: Jan Bobek <jan.bobek@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Jan Bobek" <jan.bobek@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [Qemu-devel] [RFC PATCH v3 34/46] target/i386: introduce instruction translator macros
Date: Wed, 14 Aug 2019 22:09:16 -0400 [thread overview]
Message-ID: <20190815020928.9679-35-jan.bobek@gmail.com> (raw)
In-Reply-To: <20190815020928.9679-1-jan.bobek@gmail.com>
Instruction "translators" are responsible for decoding and loading
instruction operands, calling the passed-in code generator, and
storing the operands back (if applicable). Once a translator returns,
the instruction has been translated to TCG ops, hence the name.
Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
target/i386/translate.c | 237 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 237 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 75652afb45..76c27d0380 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -5364,6 +5364,228 @@ INSNOP_LDST(xmm_t0, Mhq)
tcg_gen_gvec_ ## gvec(vece, arg1, arg2, arg3, oprsz, maxsz); \
}
+/*
+ * Instruction translators
+ */
+#define translate_insn(argc, ...) \
+ glue(translate_insn, argc)(__VA_ARGS__)
+#define translate_insn0() \
+ translate_insn_0
+#define translate_insn1(opT1) \
+ translate_insn_1 ## opT1
+#define translate_insn2(opT1, opT2) \
+ translate_insn_2 ## opT1 ## opT2
+#define translate_insn3(opT1, opT2, opT3) \
+ translate_insn_3 ## opT1 ## opT2 ## opT3
+#define translate_insn4(opT1, opT2, opT3, opT4) \
+ translate_insn_4 ## opT1 ## opT2 ## opT3 ## opT4
+#define translate_group(grpname) \
+ translate_group_ ## grpname
+
+static void translate_insn0()(
+ CPUX86State *env, DisasContext *s, int modrm,
+ int ck_cpuid_feat, unsigned int argc_wr,
+ void (*gen_insn_fp)(CPUX86State *, DisasContext *))
+{
+ if (ck_cpuid(env, s, ck_cpuid_feat)) {
+ gen_illegal_opcode(s);
+ return;
+ }
+
+ (*gen_insn_fp)(env, s);
+}
+
+#define DEF_TRANSLATE_INSN1(opT1) \
+ static void translate_insn1(opT1)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ int ck_cpuid_feat, unsigned int argc_wr, \
+ void (*gen_insn1_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ \
+ int ret = ck_cpuid(env, s, ck_cpuid_feat); \
+ if (!ret) { \
+ ret = insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ } \
+ if (!ret) { \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ \
+ (*gen_insn1_fp)(env, s, arg1); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN2(opT1, opT2) \
+ static void translate_insn2(opT1, opT2)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ int ck_cpuid_feat, unsigned int argc_wr, \
+ void (*gen_insn2_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ \
+ int ret = ck_cpuid(env, s, ck_cpuid_feat); \
+ if (!ret) { \
+ ret = insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ } \
+ if (!ret) { \
+ ret = insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ } \
+ if (!ret) { \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ \
+ (*gen_insn2_fp)(env, s, arg1, arg2); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN3(opT1, opT2, opT3) \
+ static void translate_insn3(opT1, opT2, opT3)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ int ck_cpuid_feat, unsigned int argc_wr, \
+ void (*gen_insn3_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ \
+ int ret = ck_cpuid(env, s, ck_cpuid_feat); \
+ if (!ret) { \
+ ret = insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ } \
+ if (!ret) { \
+ ret = insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ } \
+ if (!ret) { \
+ ret = insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ } \
+ if (!ret) { \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ \
+ (*gen_insn3_fp)(env, s, arg1, arg2, arg3); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define DEF_TRANSLATE_INSN4(opT1, opT2, opT3, opT4) \
+ static void translate_insn4(opT1, opT2, opT3, opT4)( \
+ CPUX86State *env, DisasContext *s, int modrm, \
+ int ck_cpuid_feat, unsigned int argc_wr, \
+ void (*gen_insn4_fp)(CPUX86State *, DisasContext *, \
+ insnop_arg_t(opT1), insnop_arg_t(opT2), \
+ insnop_arg_t(opT3), insnop_arg_t(opT4))) \
+ { \
+ insnop_ctxt_t(opT1) ctxt1; \
+ insnop_ctxt_t(opT2) ctxt2; \
+ insnop_ctxt_t(opT3) ctxt3; \
+ insnop_ctxt_t(opT4) ctxt4; \
+ \
+ const bool is_write1 = (1 <= argc_wr); \
+ const bool is_write2 = (2 <= argc_wr); \
+ const bool is_write3 = (3 <= argc_wr); \
+ const bool is_write4 = (4 <= argc_wr); \
+ \
+ int ret = ck_cpuid(env, s, ck_cpuid_feat); \
+ if (!ret) { \
+ ret = insnop_init(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ } \
+ if (!ret) { \
+ ret = insnop_init(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ } \
+ if (!ret) { \
+ ret = insnop_init(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ } \
+ if (!ret) { \
+ ret = insnop_init(opT4)(&ctxt4, env, s, modrm, is_write4); \
+ } \
+ if (!ret) { \
+ const insnop_arg_t(opT1) arg1 = \
+ insnop_prepare(opT1)(&ctxt1, env, s, modrm, is_write1); \
+ const insnop_arg_t(opT2) arg2 = \
+ insnop_prepare(opT2)(&ctxt2, env, s, modrm, is_write2); \
+ const insnop_arg_t(opT3) arg3 = \
+ insnop_prepare(opT3)(&ctxt3, env, s, modrm, is_write3); \
+ const insnop_arg_t(opT4) arg4 = \
+ insnop_prepare(opT4)(&ctxt4, env, s, modrm, is_write4); \
+ \
+ (*gen_insn4_fp)(env, s, arg1, arg2, arg3, arg4); \
+ \
+ insnop_finalize(opT1)(&ctxt1, env, s, modrm, is_write1, arg1); \
+ insnop_finalize(opT2)(&ctxt2, env, s, modrm, is_write2, arg2); \
+ insnop_finalize(opT3)(&ctxt3, env, s, modrm, is_write3, arg3); \
+ insnop_finalize(opT4)(&ctxt4, env, s, modrm, is_write4, arg4); \
+ } else { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+
+#define OPCODE_GRP_BEGIN(grpname) \
+ static void translate_group(grpname)( \
+ CPUX86State *env, DisasContext *s, int modrm) \
+ { \
+ insnop_ctxt_t(modrm_reg) regctxt; \
+ \
+ int ret = insnop_init(modrm_reg)(®ctxt, env, s, modrm, 0); \
+ if (!ret) { \
+ const insnop_arg_t(modrm_reg) reg = \
+ insnop_prepare(modrm_reg)(®ctxt, env, s, modrm, 0); \
+ \
+ switch (reg & 7) {
+#define OPCODE_GRPMEMB(grpname, mnem, opcode, feat, fmt, ...) \
+ case opcode: \
+ translate_insn(FMT_ARGC(fmt), ## __VA_ARGS__)( \
+ env, s, modrm, CK_CPUID_ ## feat, FMT_ARGC_WR(fmt), \
+ gen_insn(mnem, FMT_ARGC(fmt), ## __VA_ARGS__)); \
+ break;
+#define OPCODE_GRP_END(grpname) \
+ default: \
+ ret = 1; \
+ break; \
+ } \
+ \
+ insnop_finalize(modrm_reg)(®ctxt, env, s, modrm, 0, reg); \
+ } \
+ \
+ if (ret) { \
+ gen_illegal_opcode(s); \
+ } \
+ }
+#include "sse-opcode.inc.h"
+
static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
{
enum {
@@ -5383,6 +5605,21 @@ static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
| (s->prefix & PREFIX_REPNZ ? P_F2 : 0)
| (REX_W(s) > 0 ? W_1 : W_0)) {
+#define LEG(p, m, w, opcode) \
+ case opcode | M_ ## m | P_ ## p | W_ ## w:
+#define OPCODE(mnem, cases, feat, fmt, ...) \
+ cases { \
+ const int modrm = 0 < FMT_ARGC(fmt) ? x86_ldub_code(env, s) : -1; \
+ translate_insn(FMT_ARGC(fmt), ## __VA_ARGS__)( \
+ env, s, modrm, CK_CPUID_ ## feat, FMT_ARGC_WR(fmt), \
+ gen_insn(mnem, FMT_ARGC(fmt), ## __VA_ARGS__)); \
+ } return;
+#define OPCODE_GRP(grpname, cases) \
+ cases { \
+ const int modrm = x86_ldub_code(env, s); \
+ translate_group(grpname)(env, s, modrm); \
+ } return;
+#include "sse-opcode.inc.h"
default:
gen_sse(env, s, b);
return;
--
2.20.1
next prev parent reply other threads:[~2019-08-15 2:38 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-15 2:08 [Qemu-devel] [RFC PATCH v3 00/46] rewrite MMX/SSE/SSE2/SSE3 instruction translation Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 01/46] target/i386: Push rex_r into DisasContext Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 02/46] target/i386: Push rex_w " Jan Bobek
2019-08-15 7:30 ` Aleksandar Markovic
2019-08-15 9:55 ` Richard Henderson
2019-08-15 10:19 ` Aleksandar Markovic
2019-08-21 5:12 ` Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 03/46] target/i386: reduce scope of variable aflag Jan Bobek
2019-08-15 7:16 ` Aleksandar Markovic
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 04/46] target/i386: use dflag from DisasContext Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 05/46] target/i386: use prefix " Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 06/46] target/i386: Simplify gen_exception arguments Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 07/46] target/i386: use pc_start from DisasContext Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 08/46] target/i386: make variable b1 const Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 09/46] target/i386: make variable is_xmm const Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 10/46] target/i386: add vector register file alignment constraints Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 11/46] target/i386: introduce gen_(ld, st)d_env_A0 Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 12/46] target/i386: introduce gen_sse_ng Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 13/46] target/i386: disable unused function warning temporarily Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 14/46] target/i386: introduce mnemonic aliases for several gvec operations Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 15/46] target/i386: introduce function ck_cpuid Jan Bobek
2019-08-15 15:01 ` Aleksandar Markovic
2019-08-15 15:16 ` Richard Henderson
2019-08-21 5:07 ` Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 16/46] target/i386: introduce instruction operand infrastructure Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 17/46] target/i386: introduce generic operand alias Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 18/46] target/i386: introduce generic either-or operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 19/46] target/i386: introduce generic load-store operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 20/46] target/i386: introduce tcg_temp operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 21/46] target/i386: introduce modrm operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 22/46] target/i386: introduce operands for decoding modrm fields Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 23/46] target/i386: introduce operand for direct-only r/m field Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 24/46] target/i386: introduce operand vex_v Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 25/46] target/i386: introduce Ib (immediate) operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 26/46] target/i386: introduce M* (memptr) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 27/46] target/i386: introduce G*, R*, E* (general register) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 28/46] target/i386: introduce P*, N*, Q* (MMX) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 29/46] target/i386: introduce H*, V*, U*, W* (SSE/AVX) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 30/46] target/i386: introduce code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 31/46] target/i386: introduce helper-based code generator macros Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 32/46] target/i386: introduce gvec-based " Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 33/46] target/i386: introduce sse-opcode.inc.h Jan Bobek
2019-08-15 2:09 ` Jan Bobek [this message]
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 35/46] target/i386: introduce MMX translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 36/46] target/i386: introduce MMX code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 37/46] target/i386: introduce MMX instructions to sse-opcode.inc.h Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 38/46] target/i386: introduce SSE translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 39/46] target/i386: introduce SSE code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 40/46] target/i386: introduce SSE instructions to sse-opcode.inc.h Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 41/46] target/i386: introduce SSE2 translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 42/46] target/i386: introduce SSE2 code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 43/46] target/i386: introduce SSE2 instructions to sse-opcode.inc.h Jan Bobek
2019-08-15 8:00 ` Aleksandar Markovic
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 44/46] target/i386: introduce SSE3 translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 45/46] target/i386: introduce SSE3 code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 46/46] target/i386: introduce SSE3 instructions to sse-opcode.inc.h Jan Bobek
[not found] ` <CAL1e-=gZF1+=Gduqm4TwS0p-G6rvb4q+rw+hL9nzAz3P-r3+BQ@mail.gmail.com>
2019-08-15 9:49 ` Richard Henderson
2019-08-15 10:07 ` Aleksandar Markovic
2019-08-21 5:04 ` Jan Bobek
2019-08-15 3:06 ` [Qemu-devel] [RFC PATCH v3 00/46] rewrite MMX/SSE/SSE2/SSE3 instruction translation no-reply
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