From: Jan Bobek <jan.bobek@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Jan Bobek" <jan.bobek@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>
Subject: [Qemu-devel] [RFC PATCH v3 37/46] target/i386: introduce MMX instructions to sse-opcode.inc.h
Date: Wed, 14 Aug 2019 22:09:19 -0400 [thread overview]
Message-ID: <20190815020928.9679-38-jan.bobek@gmail.com> (raw)
In-Reply-To: <20190815020928.9679-1-jan.bobek@gmail.com>
Add all MMX instruction entries to sse-opcode.inc.h.
Signed-off-by: Jan Bobek <jan.bobek@gmail.com>
---
target/i386/sse-opcode.inc.h | 131 +++++++++++++++++++++++++++++++++++
1 file changed, 131 insertions(+)
diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h
index c5e81a6a80..36963e5a7c 100644
--- a/target/i386/sse-opcode.inc.h
+++ b/target/i386/sse-opcode.inc.h
@@ -39,6 +39,137 @@
# define OPCODE_GRP_END(grpname)
#endif /* OPCODE_GRP_END */
+/* NP 0F 6E /r: MOVD mm,r/m32 */
+OPCODE(movd, LEG(NP, 0F, 0, 0x6e), MMX, WR, Pq, Ed)
+/* NP 0F 7E /r: MOVD r/m32,mm */
+OPCODE(movd, LEG(NP, 0F, 0, 0x7e), MMX, WR, Ed, Pq)
+/* NP REX.W + 0F 6E /r: MOVQ mm,r/m64 */
+OPCODE(movq, LEG(NP, 0F, 1, 0x6e), MMX, WR, Pq, Eq)
+/* NP REX.W + 0F 7E /r: MOVQ r/m64,mm */
+OPCODE(movq, LEG(NP, 0F, 1, 0x7e), MMX, WR, Eq, Pq)
+/* NP 0F 6F /r: MOVQ mm, mm/m64 */
+OPCODE(movq, LEG(NP, 0F, 0, 0x6f), MMX, WR, Pq, Qq)
+/* NP 0F 7F /r: MOVQ mm/m64, mm */
+OPCODE(movq, LEG(NP, 0F, 0, 0x7f), MMX, WR, Qq, Pq)
+/* NP 0F FC /r: PADDB mm, mm/m64 */
+OPCODE(paddb, LEG(NP, 0F, 0, 0xfc), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F FD /r: PADDW mm, mm/m64 */
+OPCODE(paddw, LEG(NP, 0F, 0, 0xfd), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F FE /r: PADDD mm, mm/m64 */
+OPCODE(paddd, LEG(NP, 0F, 0, 0xfe), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F EC /r: PADDSB mm, mm/m64 */
+OPCODE(paddsb, LEG(NP, 0F, 0, 0xec), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F ED /r: PADDSW mm, mm/m64 */
+OPCODE(paddsw, LEG(NP, 0F, 0, 0xed), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F DC /r: PADDUSB mm,mm/m64 */
+OPCODE(paddusb, LEG(NP, 0F, 0, 0xdc), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F DD /r: PADDUSW mm,mm/m64 */
+OPCODE(paddusw, LEG(NP, 0F, 0, 0xdd), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F F8 /r: PSUBB mm, mm/m64 */
+OPCODE(psubb, LEG(NP, 0F, 0, 0xf8), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F F9 /r: PSUBW mm, mm/m64 */
+OPCODE(psubw, LEG(NP, 0F, 0, 0xf9), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F FA /r: PSUBD mm, mm/m64 */
+OPCODE(psubd, LEG(NP, 0F, 0, 0xfa), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F E8 /r: PSUBSB mm, mm/m64 */
+OPCODE(psubsb, LEG(NP, 0F, 0, 0xe8), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F E9 /r: PSUBSW mm, mm/m64 */
+OPCODE(psubsw, LEG(NP, 0F, 0, 0xe9), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F D8 /r: PSUBUSB mm, mm/m64 */
+OPCODE(psubusb, LEG(NP, 0F, 0, 0xd8), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F D9 /r: PSUBUSW mm, mm/m64 */
+OPCODE(psubusw, LEG(NP, 0F, 0, 0xd9), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F D5 /r: PMULLW mm, mm/m64 */
+OPCODE(pmullw, LEG(NP, 0F, 0, 0xd5), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F E5 /r: PMULHW mm, mm/m64 */
+OPCODE(pmulhw, LEG(NP, 0F, 0, 0xe5), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F F5 /r: PMADDWD mm, mm/m64 */
+OPCODE(pmaddwd, LEG(NP, 0F, 0, 0xf5), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 74 /r: PCMPEQB mm,mm/m64 */
+OPCODE(pcmpeqb, LEG(NP, 0F, 0, 0x74), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 75 /r: PCMPEQW mm,mm/m64 */
+OPCODE(pcmpeqw, LEG(NP, 0F, 0, 0x75), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 76 /r: PCMPEQD mm,mm/m64 */
+OPCODE(pcmpeqd, LEG(NP, 0F, 0, 0x76), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 64 /r: PCMPGTB mm,mm/m64 */
+OPCODE(pcmpgtb, LEG(NP, 0F, 0, 0x64), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 65 /r: PCMPGTW mm,mm/m64 */
+OPCODE(pcmpgtw, LEG(NP, 0F, 0, 0x65), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 66 /r: PCMPGTD mm,mm/m64 */
+OPCODE(pcmpgtd, LEG(NP, 0F, 0, 0x66), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F DB /r: PAND mm, mm/m64 */
+OPCODE(pand, LEG(NP, 0F, 0, 0xdb), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F DF /r: PANDN mm, mm/m64 */
+OPCODE(pandn, LEG(NP, 0F, 0, 0xdf), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F EB /r: POR mm, mm/m64 */
+OPCODE(por, LEG(NP, 0F, 0, 0xeb), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F EF /r: PXOR mm, mm/m64 */
+OPCODE(pxor, LEG(NP, 0F, 0, 0xef), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F F1 /r: PSLLW mm, mm/m64 */
+OPCODE(psllw, LEG(NP, 0F, 0, 0xf1), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F F2 /r: PSLLD mm, mm/m64 */
+OPCODE(pslld, LEG(NP, 0F, 0, 0xf2), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F F3 /r: PSLLQ mm, mm/m64 */
+OPCODE(psllq, LEG(NP, 0F, 0, 0xf3), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F D1 /r: PSRLW mm, mm/m64 */
+OPCODE(psrlw, LEG(NP, 0F, 0, 0xd1), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F D2 /r: PSRLD mm, mm/m64 */
+OPCODE(psrld, LEG(NP, 0F, 0, 0xd2), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F D3 /r: PSRLQ mm, mm/m64 */
+OPCODE(psrlq, LEG(NP, 0F, 0, 0xd3), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F E1 /r: PSRAW mm,mm/m64 */
+OPCODE(psraw, LEG(NP, 0F, 0, 0xe1), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F E2 /r: PSRAD mm,mm/m64 */
+OPCODE(psrad, LEG(NP, 0F, 0, 0xe2), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 63 /r: PACKSSWB mm1, mm2/m64 */
+OPCODE(packsswb, LEG(NP, 0F, 0, 0x63), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 6B /r: PACKSSDW mm1, mm2/m64 */
+OPCODE(packssdw, LEG(NP, 0F, 0, 0x6b), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 67 /r: PACKUSWB mm, mm/m64 */
+OPCODE(packuswb, LEG(NP, 0F, 0, 0x67), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 68 /r: PUNPCKHBW mm, mm/m64 */
+OPCODE(punpckhbw, LEG(NP, 0F, 0, 0x68), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 69 /r: PUNPCKHWD mm, mm/m64 */
+OPCODE(punpckhwd, LEG(NP, 0F, 0, 0x69), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 6A /r: PUNPCKHDQ mm, mm/m64 */
+OPCODE(punpckhdq, LEG(NP, 0F, 0, 0x6a), MMX, WRR, Pq, Pq, Qq)
+/* NP 0F 60 /r: PUNPCKLBW mm, mm/m32 */
+OPCODE(punpcklbw, LEG(NP, 0F, 0, 0x60), MMX, WRR, Pq, Pq, Qd)
+/* NP 0F 61 /r: PUNPCKLWD mm, mm/m32 */
+OPCODE(punpcklwd, LEG(NP, 0F, 0, 0x61), MMX, WRR, Pq, Pq, Qd)
+/* NP 0F 62 /r: PUNPCKLDQ mm, mm/m32 */
+OPCODE(punpckldq, LEG(NP, 0F, 0, 0x62), MMX, WRR, Pq, Pq, Qd)
+/* NP 0F 77: EMMS */
+OPCODE(emms, LEG(NP, 0F, 0, 0x77), MMX, )
+
+OPCODE_GRP(grp12_LEG_NP, LEG(NP, 0F, 0, 0x71))
+OPCODE_GRP_BEGIN(grp12_LEG_NP)
+ /* NP 0F 71 /6 ib: PSLLW mm1, imm8 */
+ OPCODE_GRPMEMB(grp12_LEG_NP, psllw, 6, MMX, WRR, Nq, Nq, Ib)
+ /* NP 0F 71 /2 ib: PSRLW mm, imm8 */
+ OPCODE_GRPMEMB(grp12_LEG_NP, psrlw, 2, MMX, WRR, Nq, Nq, Ib)
+ /* NP 0F 71 /4 ib: PSRAW mm,imm8 */
+ OPCODE_GRPMEMB(grp12_LEG_NP, psraw, 4, MMX, WRR, Nq, Nq, Ib)
+OPCODE_GRP_END(grp12_LEG_NP)
+
+OPCODE_GRP(grp13_LEG_NP, LEG(NP, 0F, 0, 0x72))
+OPCODE_GRP_BEGIN(grp13_LEG_NP)
+ /* NP 0F 72 /6 ib: PSLLD mm, imm8 */
+ OPCODE_GRPMEMB(grp13_LEG_NP, pslld, 6, MMX, WRR, Nq, Nq, Ib)
+ /* NP 0F 72 /2 ib: PSRLD mm, imm8 */
+ OPCODE_GRPMEMB(grp13_LEG_NP, psrld, 2, MMX, WRR, Nq, Nq, Ib)
+ /* NP 0F 72 /4 ib: PSRAD mm,imm8 */
+ OPCODE_GRPMEMB(grp13_LEG_NP, psrad, 4, MMX, WRR, Nq, Nq, Ib)
+OPCODE_GRP_END(grp13_LEG_NP)
+
+OPCODE_GRP(grp14_LEG_NP, LEG(NP, 0F, 0, 0x73))
+OPCODE_GRP_BEGIN(grp14_LEG_NP)
+ /* NP 0F 73 /6 ib: PSLLQ mm, imm8 */
+ OPCODE_GRPMEMB(grp14_LEG_NP, psllq, 6, MMX, WRR, Nq, Nq, Ib)
+ /* NP 0F 73 /2 ib: PSRLQ mm, imm8 */
+ OPCODE_GRPMEMB(grp14_LEG_NP, psrlq, 2, MMX, WRR, Nq, Nq, Ib)
+OPCODE_GRP_END(grp14_LEG_NP)
+
#undef FMTI____
#undef FMTI__R__
#undef FMTI__RR__
--
2.20.1
next prev parent reply other threads:[~2019-08-15 2:47 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-15 2:08 [Qemu-devel] [RFC PATCH v3 00/46] rewrite MMX/SSE/SSE2/SSE3 instruction translation Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 01/46] target/i386: Push rex_r into DisasContext Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 02/46] target/i386: Push rex_w " Jan Bobek
2019-08-15 7:30 ` Aleksandar Markovic
2019-08-15 9:55 ` Richard Henderson
2019-08-15 10:19 ` Aleksandar Markovic
2019-08-21 5:12 ` Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 03/46] target/i386: reduce scope of variable aflag Jan Bobek
2019-08-15 7:16 ` Aleksandar Markovic
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 04/46] target/i386: use dflag from DisasContext Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 05/46] target/i386: use prefix " Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 06/46] target/i386: Simplify gen_exception arguments Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 07/46] target/i386: use pc_start from DisasContext Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 08/46] target/i386: make variable b1 const Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 09/46] target/i386: make variable is_xmm const Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 10/46] target/i386: add vector register file alignment constraints Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 11/46] target/i386: introduce gen_(ld, st)d_env_A0 Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 12/46] target/i386: introduce gen_sse_ng Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 13/46] target/i386: disable unused function warning temporarily Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 14/46] target/i386: introduce mnemonic aliases for several gvec operations Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 15/46] target/i386: introduce function ck_cpuid Jan Bobek
2019-08-15 15:01 ` Aleksandar Markovic
2019-08-15 15:16 ` Richard Henderson
2019-08-21 5:07 ` Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 16/46] target/i386: introduce instruction operand infrastructure Jan Bobek
2019-08-15 2:08 ` [Qemu-devel] [RFC PATCH v3 17/46] target/i386: introduce generic operand alias Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 18/46] target/i386: introduce generic either-or operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 19/46] target/i386: introduce generic load-store operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 20/46] target/i386: introduce tcg_temp operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 21/46] target/i386: introduce modrm operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 22/46] target/i386: introduce operands for decoding modrm fields Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 23/46] target/i386: introduce operand for direct-only r/m field Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 24/46] target/i386: introduce operand vex_v Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 25/46] target/i386: introduce Ib (immediate) operand Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 26/46] target/i386: introduce M* (memptr) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 27/46] target/i386: introduce G*, R*, E* (general register) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 28/46] target/i386: introduce P*, N*, Q* (MMX) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 29/46] target/i386: introduce H*, V*, U*, W* (SSE/AVX) operands Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 30/46] target/i386: introduce code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 31/46] target/i386: introduce helper-based code generator macros Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 32/46] target/i386: introduce gvec-based " Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 33/46] target/i386: introduce sse-opcode.inc.h Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 34/46] target/i386: introduce instruction translator macros Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 35/46] target/i386: introduce MMX translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 36/46] target/i386: introduce MMX code generators Jan Bobek
2019-08-15 2:09 ` Jan Bobek [this message]
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 38/46] target/i386: introduce SSE translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 39/46] target/i386: introduce SSE code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 40/46] target/i386: introduce SSE instructions to sse-opcode.inc.h Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 41/46] target/i386: introduce SSE2 translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 42/46] target/i386: introduce SSE2 code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 43/46] target/i386: introduce SSE2 instructions to sse-opcode.inc.h Jan Bobek
2019-08-15 8:00 ` Aleksandar Markovic
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 44/46] target/i386: introduce SSE3 translators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 45/46] target/i386: introduce SSE3 code generators Jan Bobek
2019-08-15 2:09 ` [Qemu-devel] [RFC PATCH v3 46/46] target/i386: introduce SSE3 instructions to sse-opcode.inc.h Jan Bobek
[not found] ` <CAL1e-=gZF1+=Gduqm4TwS0p-G6rvb4q+rw+hL9nzAz3P-r3+BQ@mail.gmail.com>
2019-08-15 9:49 ` Richard Henderson
2019-08-15 10:07 ` Aleksandar Markovic
2019-08-21 5:04 ` Jan Bobek
2019-08-15 3:06 ` [Qemu-devel] [RFC PATCH v3 00/46] rewrite MMX/SSE/SSE2/SSE3 instruction translation no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190815020928.9679-38-jan.bobek@gmail.com \
--to=jan.bobek@gmail.com \
--cc=alex.bennee@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).