From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Anthony PERARD <anthony.perard@citrix.com>,
qemu-arm <qemu-arm@nongnu.org>,
Stefano Stabellini <sstabellini@kernel.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 0/2] target/arm: Take exceptions on ATS instructions
Date: Tue, 20 Aug 2019 14:59:08 +0200 [thread overview]
Message-ID: <20190820125908.GQ17732@toto> (raw)
In-Reply-To: <CAFEAcA-7Lr0nUD3g=C7S1Obgaa0E0p794XLhuBZRW_+fC5YjcQ@mail.gmail.com>
On Mon, Aug 19, 2019 at 01:44:37PM +0100, Peter Maydell wrote:
> On Fri, 16 Aug 2019 at 13:58, Peter Maydell <peter.maydell@linaro.org> wrote:
> >
> > The translation table walk for an ATS instruction can result in
> > various faults. In general these are just reported back via the
> > PAR_EL1 fault status fields, but in some cases the architecture
> > requires that the fault is turned into an exception:
> > * synchronous stage 2 faults of any kind during AT S1E0* and
> > AT S1E1* instructions executed from NS EL1 fault to EL2 or EL3
> > * synchronous external aborts are taken as Data Abort exceptions
> >
> > (This is documented in the v8A Arm ARM DDI0487A.e D5.2.11 and G5.13.4.)
> >
> > I noticed this by code inspection back last year sometime when
> > I was investigating a guest boot failure that turned out to be
> > due to an entirely different cause. I got about halfway through
> > trying to code up a fix before I realised it was irrelevant to
> > that bug. This patchset is just tidying up and completing that
> > work so it doesn't get lost.
> >
> > Use of ATS insns in the cases where they might actually fault
> > is quite rare (obviously nobody sets up page tables where there's
> > no memory and they'll take external aborts, and even for the
> > "take a hyp trap for a stage 2 fault" case you need a setup
> > with a hypervisor and a guest that uses ATS insns, and Linux as
> > a guest doesn't use ATS at all. So my testing of this patchset
> > has been more "check it doesn't break things" rather than
> > actively finding and testing a use of the throw-an-exception path...
>
> I'm told that Xen for Arm makes more active use of ATS
> instructions, so I've cc'd a few Xen people -- do any
> of you have handy testing setups to try running Xen in
> emulation under QEMU? Configs where the guest (EL1) actually
> uses ATS instructions are the particularly interesting point
> for this patchset.
>
> (if there's a good set of instructions for creating a test
> image I could probably add it to the ad-hoc set of things
> I sometimes test with.)
Hi,
All tests passed.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Cheers,
Edgar
prev parent reply other threads:[~2019-08-20 13:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-16 12:58 [Qemu-devel] [PATCH 0/2] target/arm: Take exceptions on ATS instructions Peter Maydell
2019-08-16 12:58 ` [Qemu-devel] [PATCH 1/2] target/arm: Allow ARMCPRegInfo read/write functions to throw exceptions Peter Maydell
2019-08-18 6:12 ` Richard Henderson
2019-08-27 14:47 ` Peter Maydell
2019-08-16 12:58 ` [Qemu-devel] [PATCH 2/2] target/arm: Take exceptions on ATS instructions when needed Peter Maydell
2019-08-18 6:23 ` Richard Henderson
2019-08-16 18:13 ` [Qemu-devel] [PATCH 0/2] target/arm: Take exceptions on ATS instructions no-reply
2019-08-19 12:44 ` Peter Maydell
2019-08-19 17:33 ` Edgar E. Iglesias
2019-08-20 12:59 ` Edgar E. Iglesias [this message]
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