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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 12/13] target/openrisc: Implement l.adrp
Date: Wed,  4 Sep 2019 13:45:06 -0700	[thread overview]
Message-ID: <20190904204507.32457-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org>

This was added to the 1.3 spec.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/disas.c      |  1 +
 target/openrisc/translate.c  | 13 +++++++++++++
 target/openrisc/insns.decode |  2 ++
 3 files changed, 16 insertions(+)

diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index e51cbb24c6..ce112640b9 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -98,6 +98,7 @@ INSN(sw,     "%d(r%d), r%d", a->i, a->a, a->b)
 INSN(sb,     "%d(r%d), r%d", a->i, a->a, a->b)
 INSN(sh,     "%d(r%d), r%d", a->i, a->a, a->b)
 INSN(nop,    "")
+INSN(adrp,   "r%d, %d", a->d, a->i)
 INSN(addi,   "r%d, r%d, %d", a->d, a->a, a->i)
 INSN(addic,  "r%d, r%d, %d", a->d, a->a, a->i)
 INSN(muli,   "r%d, r%d, %d", a->d, a->a, a->i)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 6e8bc23568..6addbac8d6 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -799,6 +799,19 @@ static bool trans_l_nop(DisasContext *dc, arg_l_nop *a)
     return true;
 }
 
+static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a)
+{
+    if (!check_v1_3(dc)) {
+        return false;
+    }
+    check_r0_write(dc, a->d);
+
+    tcg_gen_movi_i32(cpu_R(dc, a->d),
+                     (dc->base.pc_next & TARGET_PAGE_MASK) +
+                     ((target_long)a->i << TARGET_PAGE_BITS));
+    return true;
+}
+
 static bool trans_l_addi(DisasContext *dc, arg_rri *a)
 {
     TCGv t0;
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 71e0d740db..0d6f7c29f8 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -102,6 +102,8 @@ l_maci          010011 ----- a:5 i:s16
 l_movhi         000110 d:5 ----0 k:16
 l_macrc         000110 d:5 ----1 00000000 00000000
 
+l_adrp          000010 d:5 i:s21
+
 ####
 # Arithmetic Instructions
 ####
-- 
2.17.1



  parent reply	other threads:[~2019-09-04 21:39 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-04 20:44 [Qemu-devel] [PULL 00/13] target/openrisc updates Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 01/13] target/openrisc: Add DisasContext parameter to check_r0_write Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 02/13] target/openrisc: Replace cpu register array with a function Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 03/13] target/openrisc: Cache R0 in DisasContext Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 04/13] target/openrisc: Make VR and PPC read-only Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 06/13] target/openrisc: Add VR2 and AVR special processor registers Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 07/13] target/openrisc: Fix lf.ftoi.s Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 08/13] target/openrisc: Check CPUCFG_OF32S for float insns Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 09/13] target/openrisc: Add support for ORFPX64A32 Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 10/13] target/openrisc: Implement unordered fp comparisons Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 11/13] target/openrisc: Implement move to/from FPCSR Richard Henderson
2019-09-04 20:45 ` Richard Henderson [this message]
2019-09-04 20:45 ` [Qemu-devel] [PULL 13/13] target/openrisc: Update cpu "any" to v1.3 Richard Henderson
2019-09-05  9:25 ` [Qemu-devel] [PULL 00/13] target/openrisc updates Peter Maydell

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