From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 13/13] target/openrisc: Update cpu "any" to v1.3
Date: Wed, 4 Sep 2019 13:45:07 -0700 [thread overview]
Message-ID: <20190904204507.32457-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org>
Now that the two updates from v1.3 are implemented,
update the "any" cpu to enable it.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f96a69e278..506aec6bfb 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -129,7 +129,7 @@ static void openrisc_any_initfn(Object *obj)
cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */
cpu->env.vr2 = 0; /* No version specific id */
- cpu->env.avr = 0x01010000; /* Architecture v1.1 */
+ cpu->env.avr = 0x01030000; /* Architecture v1.3 */
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
--
2.17.1
next prev parent reply other threads:[~2019-09-04 21:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-04 20:44 [Qemu-devel] [PULL 00/13] target/openrisc updates Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 01/13] target/openrisc: Add DisasContext parameter to check_r0_write Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 02/13] target/openrisc: Replace cpu register array with a function Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 03/13] target/openrisc: Cache R0 in DisasContext Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 04/13] target/openrisc: Make VR and PPC read-only Richard Henderson
2019-09-04 20:44 ` [Qemu-devel] [PULL 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 06/13] target/openrisc: Add VR2 and AVR special processor registers Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 07/13] target/openrisc: Fix lf.ftoi.s Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 08/13] target/openrisc: Check CPUCFG_OF32S for float insns Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 09/13] target/openrisc: Add support for ORFPX64A32 Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 10/13] target/openrisc: Implement unordered fp comparisons Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 11/13] target/openrisc: Implement move to/from FPCSR Richard Henderson
2019-09-04 20:45 ` [Qemu-devel] [PULL 12/13] target/openrisc: Implement l.adrp Richard Henderson
2019-09-04 20:45 ` Richard Henderson [this message]
2019-09-05 9:25 ` [Qemu-devel] [PULL 00/13] target/openrisc updates Peter Maydell
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