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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id n66sm8104610pfn.90.2019.09.04.13.45.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Sep 2019 13:45:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:44:59 -0700 Message-Id: <20190904204507.32457-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 Subject: [Qemu-devel] [PULL 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" These registers are read-only and implementation specific. Initiailize VR for the first time; take the OR1200 values from the verilog source. Note that moving fields within CPUOpenRISCState does not affect migration. Reviewed-by: Stafford Horne Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 8 ++++---- target/openrisc/cpu.c | 23 ++++++++++++++++------- target/openrisc/sys_helper.c | 4 ++-- 3 files changed, 22 insertions(+), 13 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 755282f95d..18d7445e74 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState { target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ - uint32_t vr; /* Version register */ - uint32_t upr; /* Unit presence register */ - uint32_t dmmucfgr; /* DMMU configure register */ - uint32_t immucfgr; /* IMMU configure register */ uint32_t esr; /* Exception supervisor register */ uint32_t evbar; /* Exception vector base address register */ uint32_t pmr; /* Power Management Register */ @@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState { struct {} end_reset_fields; /* Fields from here on are preserved across CPU reset. */ + uint32_t vr; /* Version register */ + uint32_t upr; /* Unit presence register */ uint32_t cpucfgr; /* CPU configure register */ + uint32_t dmmucfgr; /* DMMU configure register */ + uint32_t immucfgr; /* IMMU configure register */ #ifndef CONFIG_USER_ONLY QEMUTimer *timer; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f19e482a55..d9f447e90c 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -56,13 +56,6 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr = -1; s->exception_index = -1; - cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | - UPR_PMP; - cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) - | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); - cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) - | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); - #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; cpu->env.picsr = 0x00000000; @@ -117,15 +110,31 @@ static void or1200_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); + cpu->env.vr = 0x13000008; + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_EVBARP; + + /* 1Way, TLB_SIZE entries. */ + cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } static void openrisc_any_initfn(Object *obj) { OpenRISCCPU *cpu = OPENRISC_CPU(obj); + cpu->env.vr = 0x13000000; + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP; + + /* 1Way, TLB_SIZE entries. */ + cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) + | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); + cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) + | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } static void openrisc_cpu_class_init(ObjectClass *oc, void *data) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index d20f48b659..a2b1f52294 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -199,13 +199,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, return env->vr; case TO_SPR(0, 1): /* UPR */ - return env->upr; /* TT, DM, IM, UP present */ + return env->upr; case TO_SPR(0, 2): /* CPUCFGR */ return env->cpucfgr; case TO_SPR(0, 3): /* DMMUCFGR */ - return env->dmmucfgr; /* 1Way, 64 entries */ + return env->dmmucfgr; case TO_SPR(0, 4): /* IMMUCFGR */ return env->immucfgr; -- 2.17.1