From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 989B2C3A59E for ; Wed, 4 Sep 2019 21:52:12 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6EBCC20828 for ; Wed, 4 Sep 2019 21:52:12 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6EBCC20828 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:40554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5dCF-0002q6-Hp for qemu-devel@archiver.kernel.org; Wed, 04 Sep 2019 17:52:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53565) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cCO-0000kB-3x for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cCM-0001j8-S9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:15 -0400 Received: from 2.mo2.mail-out.ovh.net ([188.165.53.149]:33973) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cCM-0001iQ-M2 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:48:14 -0400 Received: from player691.ha.ovh.net (unknown [10.109.159.224]) by mo2.mail-out.ovh.net (Postfix) with ESMTP id 53A671AB3A5 for ; Wed, 4 Sep 2019 22:48:13 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id A2E0998B289E; Wed, 4 Sep 2019 20:48:06 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:53 +0200 Message-Id: <20190904204659.13878-10-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Ovh-Tracer-Id: 2525674966197504785 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 188.165.53.149 Subject: [Qemu-devel] [RFC PATCH 09/15] hw: wdt_aspeed: Add AST2600 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Joel Stanley The AST2600 has four watchdogs, and they each have a 0x40 of registers. When running as part of an ast2600 system we must check a different offset for the system reset control register in the SCU. Signed-off-by: Joel Stanley [clg: - reworked mode integration into new objet class ] Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 2 +- include/hw/watchdog/wdt_aspeed.h | 1 + hw/watchdog/wdt_aspeed.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index ba5bbb53e1a1..b427f2668a8a 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -27,7 +27,7 @@ #include "hw/sd/aspeed_sdhci.h" =20 #define ASPEED_SPIS_NUM 2 -#define ASPEED_WDTS_NUM 3 +#define ASPEED_WDTS_NUM 4 #define ASPEED_CPUS_NUM 2 #define ASPEED_MACS_NUM 2 =20 diff --git a/include/hw/watchdog/wdt_aspeed.h b/include/hw/watchdog/wdt_a= speed.h index 796342764e2e..dfedd7662dd1 100644 --- a/include/hw/watchdog/wdt_aspeed.h +++ b/include/hw/watchdog/wdt_aspeed.h @@ -18,6 +18,7 @@ OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT) #define TYPE_ASPEED_2400_WDT TYPE_ASPEED_WDT "-ast2400" #define TYPE_ASPEED_2500_WDT TYPE_ASPEED_WDT "-ast2500" +#define TYPE_ASPEED_2600_WDT TYPE_ASPEED_WDT "-ast2600" =20 #define ASPEED_WDT_REGS_MAX (0x20 / 4) =20 diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 9e241b7c8da4..6870dcf0c107 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -40,12 +40,14 @@ #define WDT_DRIVE_TYPE_MASK (0xFF << 24) #define WDT_PUSH_PULL_MAGIC (0xA8 << 24) #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24) +#define WDT_RESET_MASK1 (0x1c / 4) =20 #define WDT_TIMEOUT_STATUS (0x10 / 4) #define WDT_TIMEOUT_CLEAR (0x14 / 4) =20 #define WDT_RESTART_MAGIC 0x4755 =20 +#define AST2600_SCU_RESET_CONTROL1 (0x40 / 4) #define SCU_RESET_CONTROL1 (0x04 / 4) #define SCU_RESET_SDRAM BIT(0) =20 @@ -74,6 +76,8 @@ static uint64_t aspeed_wdt_read(void *opaque, hwaddr of= fset, unsigned size) return s->regs[WDT_CTRL]; case WDT_RESET_WIDTH: return s->regs[WDT_RESET_WIDTH]; + case WDT_RESET_MASK1: + return s->regs[WDT_RESET_MASK1]; case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -146,6 +150,11 @@ static void aspeed_wdt_write(void *opaque, hwaddr of= fset, uint64_t data, s->regs[WDT_RESET_WIDTH] |=3D data & awc->ext_pulse_width_mask; break; =20 + case WDT_RESET_MASK1: + /* TODO: implement */ + s->regs[WDT_RESET_MASK1] =3D data; + break; + case WDT_TIMEOUT_STATUS: case WDT_TIMEOUT_CLEAR: qemu_log_mask(LOG_UNIMP, @@ -316,12 +325,32 @@ static const TypeInfo aspeed_2500_wdt_info =3D { .class_init =3D aspeed_2500_wdt_class_init, }; =20 +static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedWDTClass *awc =3D ASPEED_WDT_CLASS(klass); + + dc->desc =3D "ASPEED 2600 Watchdog Controller"; + awc->offset =3D 0x40; + awc->ext_pulse_width_mask =3D 0xfffff; /* TODO */ + awc->reset_ctrl_reg =3D AST2600_SCU_RESET_CONTROL1; + awc->reset_pulse =3D aspeed_2500_wdt_reset_pulse; +} + +static const TypeInfo aspeed_2600_wdt_info =3D { + .name =3D TYPE_ASPEED_2600_WDT, + .parent =3D TYPE_ASPEED_WDT, + .instance_size =3D sizeof(AspeedWDTState), + .class_init =3D aspeed_2600_wdt_class_init, +}; + static void wdt_aspeed_register_types(void) { watchdog_add_model(&model); type_register_static(&aspeed_wdt_info); type_register_static(&aspeed_2400_wdt_info); type_register_static(&aspeed_2500_wdt_info); + type_register_static(&aspeed_2600_wdt_info); } =20 type_init(wdt_aspeed_register_types) --=20 2.21.0