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From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
	"Cédric Le Goater" <clg@kaod.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	"Joel Stanley" <joel@jms.id.au>
Subject: [Qemu-devel] [RFC PATCH 13/15] aspeed: Parameterise number of MACs
Date: Wed,  4 Sep 2019 22:46:57 +0200	[thread overview]
Message-ID: <20190904204659.13878-14-clg@kaod.org> (raw)
In-Reply-To: <20190904204659.13878-1-clg@kaod.org>

From: Joel Stanley <joel@jms.id.au>

To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h | 5 ++++-
 hw/arm/aspeed_soc.c         | 7 ++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 74db48374531..30b67a09f13c 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -30,7 +30,7 @@
 #define ASPEED_SPIS_NUM  2
 #define ASPEED_WDTS_NUM  4
 #define ASPEED_CPUS_NUM  2
-#define ASPEED_MACS_NUM  2
+#define ASPEED_MACS_NUM  4
 
 typedef struct AspeedSoCState {
     /*< private >*/
@@ -67,6 +67,7 @@ typedef struct AspeedSoCInfo {
     uint64_t sram_size;
     int spis_num;
     int wdts_num;
+    int macs_num;
     const int *irqmap;
     const hwaddr *memmap;
     uint32_t num_cpus;
@@ -117,6 +118,8 @@ enum {
     ASPEED_I2C,
     ASPEED_ETH1,
     ASPEED_ETH2,
+    ASPEED_ETH3,
+    ASPEED_ETH4,
     ASPEED_SDRAM,
     ASPEED_XDMA,
 };
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 80d7f206004c..8069de8d5a36 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -90,7 +90,9 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_SPI1]      = 0x1E630000,
     [ASPEED_SPI2]      = 0x1E641000,
     [ASPEED_ETH1]      = 0x1E660000,
+    [ASPEED_ETH3]      = 0x1E670000,
     [ASPEED_ETH2]      = 0x1E680000,
+    [ASPEED_ETH4]      = 0x1E690000,
     [ASPEED_VIC]       = 0x1E6C0000,
     [ASPEED_SDMC]      = 0x1E6E0000,
     [ASPEED_SCU]       = 0x1E6E2000,
@@ -190,6 +192,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
         .sram_size    = 0x8000,
         .spis_num     = 1,
         .wdts_num     = 2,
+        .macs_num     = 2,
         .irqmap       = aspeed_soc_ast2400_irqmap,
         .memmap       = aspeed_soc_ast2400_memmap,
         .num_cpus     = 1,
@@ -200,6 +203,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
         .sram_size    = 0x9000,
         .spis_num     = 2,
         .wdts_num     = 3,
+        .macs_num     = 2,
         .irqmap       = aspeed_soc_ast2500_irqmap,
         .memmap       = aspeed_soc_ast2500_memmap,
         .num_cpus     = 1,
@@ -210,6 +214,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
         .sram_size    = 0x10000,
         .spis_num     = 2,
         .wdts_num     = 4,
+        .macs_num     = 4,
         .irqmap       = aspeed_soc_ast2600_irqmap,
         .memmap       = aspeed_soc_ast2600_memmap,
         .num_cpus     = 2,
@@ -305,7 +310,7 @@ static void aspeed_soc_init(Object *obj)
                                        OBJECT(&s->scu), &error_abort);
     }
 
-    for (i = 0; i < ASPEED_MACS_NUM; i++) {
+    for (i = 0; i < sc->info->macs_num; i++) {
         sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
                               sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
     }
-- 
2.21.0



  parent reply	other threads:[~2019-09-04 21:52 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-04 20:46 [Qemu-devel] [RFC PATCH 00/15] aspeed: Add support for the AST2600 SoC Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 01/15] hw: aspeed_scu: Add AST2600 support Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 02/15] aspeed/timer: Introduce an object class per SoC Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 03/15] aspeed/timer: Add support for control register 3 Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 04/15] aspeed/timer: Add support for AST2600 Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 05/15] aspeed/timer: Add support for IRQ status register on the AST2600 Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 06/15] aspeed/sdmc: Introduce an object class per SoC Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 07/15] aspeed/sdmc: Add AST2600 support Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 08/15] watchdog/aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 09/15] hw: wdt_aspeed: Add AST2600 support Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 10/15] aspeed/smc: Add support for the AST2600 SoC Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 11/15] hw/gpio: Add in AST2600 specific implementation Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 12/15] aspeed: add support for the AST2600 eval board Cédric Le Goater
2019-09-04 20:46 ` Cédric Le Goater [this message]
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 14/15] aspeed: add support for the Aspeed MII controller of the AST2600 Cédric Le Goater
2019-09-04 20:46 ` [Qemu-devel] [RFC PATCH 15/15] aspeed/soc: Add ASPEED Video stub Cédric Le Goater

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