From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F400EC3A5A9 for ; Wed, 4 Sep 2019 21:29:47 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C6C6420657 for ; Wed, 4 Sep 2019 21:29:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C6C6420657 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:40208 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cqY-0003nS-9J for qemu-devel@archiver.kernel.org; Wed, 04 Sep 2019 17:29:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53347) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i5cBj-0008ND-63 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:47:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i5cBh-0000q3-Tg for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:47:35 -0400 Received: from 3.mo7.mail-out.ovh.net ([46.105.34.113]:59746) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i5cBh-0000ow-M9 for qemu-devel@nongnu.org; Wed, 04 Sep 2019 16:47:33 -0400 Received: from player691.ha.ovh.net (unknown [10.109.160.230]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id 30EC31305D1 for ; Wed, 4 Sep 2019 22:47:32 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player691.ha.ovh.net (Postfix) with ESMTPSA id 763CD98B27EF; Wed, 4 Sep 2019 20:47:25 +0000 (UTC) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: Peter Maydell Date: Wed, 4 Sep 2019 22:46:47 +0200 Message-Id: <20190904204659.13878-4-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190904204659.13878-1-clg@kaod.org> References: <20190904204659.13878-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Ovh-Tracer-Id: 2513853021181676305 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeduvddrudejhedgudehudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.34.113 Subject: [Qemu-devel] [RFC PATCH 03/15] aspeed/timer: Add support for control register 3 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The AST2500 timer has a third control register that is used to implement a set-to-clear feature for the main control register. This models the behaviour expected by the AST2500 while maintaining the same behaviour for the AST2400. Based on previous work from Joel Stanley. Signed-off-by: C=C3=A9dric Le Goater --- include/hw/timer/aspeed_timer.h | 1 + hw/timer/aspeed_timer.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_ti= mer.h index a791fee276f4..1e0288ebc49f 100644 --- a/include/hw/timer/aspeed_timer.h +++ b/include/hw/timer/aspeed_timer.h @@ -58,6 +58,7 @@ typedef struct AspeedTimerCtrlState { =20 uint32_t ctrl; uint32_t ctrl2; + uint32_t ctrl3; AspeedTimer timers[ASPEED_TIMER_NR_TIMERS]; =20 AspeedSCUState *scu; diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index c78bc1bd2d25..d70e78a0293e 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -498,6 +498,8 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtr= lState *s, hwaddr offset) =20 switch (offset) { case 0x38: + value =3D s->ctrl3 & BIT(0); + break; case 0x3C: default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx = "\n", @@ -511,9 +513,24 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCt= rlState *s, hwaddr offset) static void aspeed_2500_timer_write(AspeedTimerCtrlState *s, hwaddr offs= et, uint64_t value) { + const uint32_t tv =3D (uint32_t)(value & 0xFFFFFFFF); + uint8_t command; + switch (offset) { case 0x38: + command =3D (value >> 1) & 0xFF; + if (command =3D=3D 0xAE) { + s->ctrl3 =3D 0x1; + } else if (command =3D=3D 0xEA) { + s->ctrl3 =3D 0x0; + } + break; case 0x3C: + if (s->ctrl3 & BIT(0)) { + aspeed_timer_set_ctrl(s, s->ctrl & ~tv); + } + break; + default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx = "\n", __func__, offset); @@ -574,6 +591,7 @@ static void aspeed_timer_reset(DeviceState *dev) } s->ctrl =3D 0; s->ctrl2 =3D 0; + s->ctrl3 =3D 0; } =20 static const VMStateDescription vmstate_aspeed_timer =3D { @@ -597,6 +615,7 @@ static const VMStateDescription vmstate_aspeed_timer_= state =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32(ctrl, AspeedTimerCtrlState), VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState), + VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState), VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState, ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_t= imer, AspeedTimer), --=20 2.21.0