From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alex.bennee@linaro.org
Subject: [PATCH 3/7] target/alpha: Fix SWCR_TRAP_ENABLE_MASK
Date: Fri, 20 Sep 2019 21:32:52 -0700 [thread overview]
Message-ID: <20190921043256.4575-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190921043256.4575-1-richard.henderson@linaro.org>
The CONFIG_USER_ONLY adjustment blindly mashed the swcr
exception enable bits into the fpcr exception disable bits.
However, fpcr_exc_enable has already converted the exception
disable bits into the exception status bits in order to make
it easier to mask status bits at runtime.
Instead, merge the swcr enable bits with the fpcr before we
convert to status bits.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/helper.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 10602fb339..e21c488aa3 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -46,19 +46,8 @@ void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val)
uint32_t fpcr = val >> 32;
uint32_t t = 0;
- t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE);
- t |= CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF);
- t |= CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF);
- t |= CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE);
- t |= CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV);
-
+ /* Record the raw value before adjusting for linux-user. */
env->fpcr = fpcr;
- env->fpcr_exc_enable = ~t & FPCR_STATUS_MASK;
-
- env->fpcr_dyn_round = rm_map[(fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIFT];
-
- env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
- env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
#ifdef CONFIG_USER_ONLY
/*
@@ -67,13 +56,29 @@ void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val)
* which point the kernel's handler would emulate and apply
* the software exception mask.
*/
+ uint32_t soft_fpcr = alpha_ieee_swcr_to_fpcr(env->swcr) >> 32;
+ fpcr |= soft_fpcr & FPCR_STATUS_MASK;
+#endif
+
+ t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE);
+ t |= CONVERT_BIT(fpcr, FPCR_UNFD, FPCR_UNF);
+ t |= CONVERT_BIT(fpcr, FPCR_OVFD, FPCR_OVF);
+ t |= CONVERT_BIT(fpcr, FPCR_DZED, FPCR_DZE);
+ t |= CONVERT_BIT(fpcr, FPCR_INVD, FPCR_INV);
+
+ env->fpcr_exc_enable = ~t & FPCR_STATUS_MASK;
+
+ env->fpcr_dyn_round = rm_map[(fpcr & FPCR_DYN_MASK) >> FPCR_DYN_SHIFT];
+
+ env->fpcr_flush_to_zero = (fpcr & FPCR_UNFD) && (fpcr & FPCR_UNDZ);
+ env->fp_status.flush_inputs_to_zero = (fpcr & FPCR_DNZ) != 0;
+#ifdef CONFIG_USER_ONLY
if (env->swcr & SWCR_MAP_DMZ) {
env->fp_status.flush_inputs_to_zero = 1;
}
if (env->swcr & SWCR_MAP_UMZ) {
env->fpcr_flush_to_zero = 1;
}
- env->fpcr_exc_enable &= ~(alpha_ieee_swcr_to_fpcr(env->swcr) >> 32);
#endif
}
--
2.17.1
next prev parent reply other threads:[~2019-09-21 4:36 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-21 4:32 [PATCH 0/7] target/alpha: Fix linux-user exception for CVTTQ Richard Henderson
2019-09-21 4:32 ` [PATCH 1/7] target/alpha: Use array for FPCR_DYN conversion Richard Henderson
2019-09-21 8:53 ` Philippe Mathieu-Daudé
2019-09-23 16:23 ` Alex Bennée
2019-09-21 4:32 ` [PATCH 2/7] target/alpha: Fix SWCR_MAP_UMZ Richard Henderson
2019-09-23 16:33 ` Alex Bennée
2019-09-21 4:32 ` Richard Henderson [this message]
2019-09-21 4:32 ` [PATCH 4/7] target/alpha: Handle SWCR_MAP_DMZ earlier Richard Henderson
2019-09-21 4:32 ` [PATCH 5/7] target/alpha: Write to fpcr_flush_to_zero once Richard Henderson
2019-09-21 8:54 ` Philippe Mathieu-Daudé
2019-09-23 16:38 ` Alex Bennée
2019-09-21 4:32 ` [PATCH 6/7] target/alpha: Mask IOV exception with INV for user-only Richard Henderson
2019-09-23 16:39 ` Alex Bennée
2019-09-21 4:32 ` [PATCH 7/7] target/alpha: Tidy helper_fp_exc_raise_s Richard Henderson
2019-09-21 8:57 ` Philippe Mathieu-Daudé
2019-09-23 16:40 ` Alex Bennée
2019-09-23 16:44 ` [PATCH 0/7] target/alpha: Fix linux-user exception for CVTTQ Alex Bennée
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