* [PATCH v3 0/2] target/i386: cpu.h marcos clean up
@ 2019-09-23 6:30 Tao Xu
2019-09-23 6:30 ` [PATCH v3 1/2] target/i386: clean up comments over 80 chars per line Tao Xu
2019-09-23 6:30 ` [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco Tao Xu
0 siblings, 2 replies; 6+ messages in thread
From: Tao Xu @ 2019-09-23 6:30 UTC (permalink / raw)
To: ehabkost, sgarzare, philmd, pbonzini, rth; +Cc: Tao Xu, qemu-devel
Add some comments, clean up comments over 80 chars per line. And there
is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD, remove
the extra enter and spaces.
Drop the duplicated definition of cpuid AVX512_VBMI marco and rename it
as CPUID_7_0_ECX_AVX512_VBMI.
Changelog:
v3:
- split the patch into 2 patches. (Suggested by Stefano Garzarella
and Eduardo Habkost)
v2:
- correct the comments over 80 chars per line. (Suggested by
Philippe Mathieu-Daudé)
Tao Xu (2):
target/i386: clean up comments over 80 chars per line
target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco
target/i386/cpu.c | 4 +-
target/i386/cpu.h | 163 +++++++++++++++++++++++-------------
target/i386/hvf/x86_cpuid.c | 2 +-
3 files changed, 109 insertions(+), 60 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 1/2] target/i386: clean up comments over 80 chars per line
2019-09-23 6:30 [PATCH v3 0/2] target/i386: cpu.h marcos clean up Tao Xu
@ 2019-09-23 6:30 ` Tao Xu
2019-09-23 8:06 ` Stefano Garzarella
2019-09-23 6:30 ` [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco Tao Xu
1 sibling, 1 reply; 6+ messages in thread
From: Tao Xu @ 2019-09-23 6:30 UTC (permalink / raw)
To: ehabkost, sgarzare, philmd, pbonzini, rth; +Cc: Tao Xu, qemu-devel
Add some comments, clean up comments over 80 chars per line. And there
is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD, remove
the extra enter and spaces.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
target/i386/cpu.h | 164 ++++++++++++++++++++++++++++++----------------
1 file changed, 107 insertions(+), 57 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5f6e3a029a..fa4c4cad79 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -641,63 +641,113 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_SVM_PAUSEFILTER (1U << 10)
#define CPUID_SVM_PFTHRESHOLD (1U << 12)
-#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
-#define CPUID_7_0_EBX_BMI1 (1U << 3)
-#define CPUID_7_0_EBX_HLE (1U << 4)
-#define CPUID_7_0_EBX_AVX2 (1U << 5)
-#define CPUID_7_0_EBX_SMEP (1U << 7)
-#define CPUID_7_0_EBX_BMI2 (1U << 8)
-#define CPUID_7_0_EBX_ERMS (1U << 9)
-#define CPUID_7_0_EBX_INVPCID (1U << 10)
-#define CPUID_7_0_EBX_RTM (1U << 11)
-#define CPUID_7_0_EBX_MPX (1U << 14)
-#define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
-#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
-#define CPUID_7_0_EBX_RDSEED (1U << 18)
-#define CPUID_7_0_EBX_ADX (1U << 19)
-#define CPUID_7_0_EBX_SMAP (1U << 20)
-#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
-#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
-#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
-#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
-#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
-#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
-#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
-#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
-#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
-#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
-#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
-
-#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
-#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
-#define CPUID_7_0_ECX_UMIP (1U << 2)
-#define CPUID_7_0_ECX_PKU (1U << 3)
-#define CPUID_7_0_ECX_OSPKE (1U << 4)
-#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
-#define CPUID_7_0_ECX_GFNI (1U << 8)
-#define CPUID_7_0_ECX_VAES (1U << 9)
-#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
-#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
-#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
-#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
-#define CPUID_7_0_ECX_LA57 (1U << 16)
-#define CPUID_7_0_ECX_RDPID (1U << 22)
-#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */
-#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */
-#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */
-
-#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
-#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
-#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
-#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
-#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/
-#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
-
-#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */
-
-#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
- do not invalidate cache */
-#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
+/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
+#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
+/* 1st Group of Advanced Bit Manipulation Extensions */
+#define CPUID_7_0_EBX_BMI1 (1U << 3)
+/* Hardware Lock Elision */
+#define CPUID_7_0_EBX_HLE (1U << 4)
+/* Intel Advanced Vector Extensions 2 */
+#define CPUID_7_0_EBX_AVX2 (1U << 5)
+/* Supervisor-mode Execution Prevention */
+#define CPUID_7_0_EBX_SMEP (1U << 7)
+/* 2nd Group of Advanced Bit Manipulation Extensions */
+#define CPUID_7_0_EBX_BMI2 (1U << 8)
+/* Enhanced REP MOVSB/STOSB */
+#define CPUID_7_0_EBX_ERMS (1U << 9)
+/* Invalidate Process-Context Identifier */
+#define CPUID_7_0_EBX_INVPCID (1U << 10)
+/* Restricted Transactional Memory */
+#define CPUID_7_0_EBX_RTM (1U << 11)
+/* Memory Protection Extension */
+#define CPUID_7_0_EBX_MPX (1U << 14)
+/* AVX-512 Foundation */
+#define CPUID_7_0_EBX_AVX512F (1U << 16)
+/* AVX-512 Doubleword & Quadword Instruction */
+#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
+/* Read Random SEED */
+#define CPUID_7_0_EBX_RDSEED (1U << 18)
+/* ADCX and ADOX instructions */
+#define CPUID_7_0_EBX_ADX (1U << 19)
+/* Supervisor Mode Access Prevention */
+#define CPUID_7_0_EBX_SMAP (1U << 20)
+/* AVX-512 Integer Fused Multiply Add */
+#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
+/* Persistent Commit */
+#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
+/* Flush a Cache Line Optimized */
+#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
+/* Cache Line Write Back */
+#define CPUID_7_0_EBX_CLWB (1U << 24)
+/* Intel Processor Trace */
+#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
+/* AVX-512 Prefetch */
+#define CPUID_7_0_EBX_AVX512PF (1U << 26)
+/* AVX-512 Exponential and Reciprocal */
+#define CPUID_7_0_EBX_AVX512ER (1U << 27)
+/* AVX-512 Conflict Detection */
+#define CPUID_7_0_EBX_AVX512CD (1U << 28)
+/* SHA1/SHA256 Instruction Extensions */
+#define CPUID_7_0_EBX_SHA_NI (1U << 29)
+/* AVX-512 Byte and Word Instructions */
+#define CPUID_7_0_EBX_AVX512BW (1U << 30)
+/* AVX-512 Vector Length Extensions */
+#define CPUID_7_0_EBX_AVX512VL (1U << 31)
+
+/* AVX-512 Vector Byte Manipulation Instruction */
+#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
+#define CPUID_7_0_ECX_VBMI (1U << 1)
+/* User-Mode Instruction Prevention */
+#define CPUID_7_0_ECX_UMIP (1U << 2)
+/* Protection Keys for User-mode Pages */
+#define CPUID_7_0_ECX_PKU (1U << 3)
+/* OS Enable Protection Keys */
+#define CPUID_7_0_ECX_OSPKE (1U << 4)
+/* Additional AVX-512 Vector Byte Manipulation Instruction */
+#define CPUID_7_0_ECX_VBMI2 (1U << 6)
+/* Galois Field New Instructions */
+#define CPUID_7_0_ECX_GFNI (1U << 8)
+/* Vector AES Instructions */
+#define CPUID_7_0_ECX_VAES (1U << 9)
+/* Carry-Less Multiplication Quadword */
+#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
+/* Vector Neural Network Instructions */
+#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
+/* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
+#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
+/* POPCNT for vectors of DW/QW */
+#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
+/* 5-level Page Tables */
+#define CPUID_7_0_ECX_LA57 (1U << 16)
+/* Read Processor ID */
+#define CPUID_7_0_ECX_RDPID (1U << 22)
+/* Cache Line Demote Instruction */
+#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
+/* Move Doubleword as Direct Store Instruction */
+#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
+/* Move 64 Bytes as Direct Store Instruction */
+#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
+
+/* AVX512 Neural Network Instructions */
+#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
+/* AVX512 Multiply Accumulation Single Precision */
+#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
+/* Speculation Control */
+#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
+/* Arch Capabilities */
+#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
+/* Core Capability */
+#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
+/* Speculative Store Bypass Disable */
+#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
+
+/* AVX512 BFloat16 Instruction */
+#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
+
+/* Write back and do not invalidate cache */
+#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
+/* Indirect Branch Prediction Barrier */
+#define CPUID_8000_0008_EBX_IBPB (1U << 12)
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
#define CPUID_XSAVE_XSAVEC (1U << 1)
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/2] target/i386: clean up comments over 80 chars per line
2019-09-23 6:30 ` [PATCH v3 1/2] target/i386: clean up comments over 80 chars per line Tao Xu
@ 2019-09-23 8:06 ` Stefano Garzarella
0 siblings, 0 replies; 6+ messages in thread
From: Stefano Garzarella @ 2019-09-23 8:06 UTC (permalink / raw)
To: Tao Xu; +Cc: qemu-devel, pbonzini, philmd, ehabkost, rth
On Mon, Sep 23, 2019 at 02:30:40PM +0800, Tao Xu wrote:
> Add some comments, clean up comments over 80 chars per line. And there
> is an extra line in comment of CPUID_8000_0008_EBX_WBNOINVD, remove
> the extra enter and spaces.
>
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> ---
> target/i386/cpu.h | 164 ++++++++++++++++++++++++++++++----------------
> 1 file changed, 107 insertions(+), 57 deletions(-)
Acked-by: Stefano Garzarella <sgarzare@redhat.com>
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 5f6e3a029a..fa4c4cad79 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -641,63 +641,113 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_SVM_PAUSEFILTER (1U << 10)
> #define CPUID_SVM_PFTHRESHOLD (1U << 12)
>
> -#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
> -#define CPUID_7_0_EBX_BMI1 (1U << 3)
> -#define CPUID_7_0_EBX_HLE (1U << 4)
> -#define CPUID_7_0_EBX_AVX2 (1U << 5)
> -#define CPUID_7_0_EBX_SMEP (1U << 7)
> -#define CPUID_7_0_EBX_BMI2 (1U << 8)
> -#define CPUID_7_0_EBX_ERMS (1U << 9)
> -#define CPUID_7_0_EBX_INVPCID (1U << 10)
> -#define CPUID_7_0_EBX_RTM (1U << 11)
> -#define CPUID_7_0_EBX_MPX (1U << 14)
> -#define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
> -#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
> -#define CPUID_7_0_EBX_RDSEED (1U << 18)
> -#define CPUID_7_0_EBX_ADX (1U << 19)
> -#define CPUID_7_0_EBX_SMAP (1U << 20)
> -#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
> -#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
> -#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
> -#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
> -#define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
> -#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
> -#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
> -#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
> -#define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
> -#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
> -#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
> -
> -#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
> -#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
> -#define CPUID_7_0_ECX_UMIP (1U << 2)
> -#define CPUID_7_0_ECX_PKU (1U << 3)
> -#define CPUID_7_0_ECX_OSPKE (1U << 4)
> -#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
> -#define CPUID_7_0_ECX_GFNI (1U << 8)
> -#define CPUID_7_0_ECX_VAES (1U << 9)
> -#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
> -#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
> -#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
> -#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
> -#define CPUID_7_0_ECX_LA57 (1U << 16)
> -#define CPUID_7_0_ECX_RDPID (1U << 22)
> -#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */
> -#define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */
> -#define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */
> -
> -#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
> -#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
> -#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
> -#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
> -#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/
> -#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
> -
> -#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) /* AVX512 BFloat16 Instruction */
> -
> -#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
> - do not invalidate cache */
> -#define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
> +/* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
> +#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
> +/* 1st Group of Advanced Bit Manipulation Extensions */
> +#define CPUID_7_0_EBX_BMI1 (1U << 3)
> +/* Hardware Lock Elision */
> +#define CPUID_7_0_EBX_HLE (1U << 4)
> +/* Intel Advanced Vector Extensions 2 */
> +#define CPUID_7_0_EBX_AVX2 (1U << 5)
> +/* Supervisor-mode Execution Prevention */
> +#define CPUID_7_0_EBX_SMEP (1U << 7)
> +/* 2nd Group of Advanced Bit Manipulation Extensions */
> +#define CPUID_7_0_EBX_BMI2 (1U << 8)
> +/* Enhanced REP MOVSB/STOSB */
> +#define CPUID_7_0_EBX_ERMS (1U << 9)
> +/* Invalidate Process-Context Identifier */
> +#define CPUID_7_0_EBX_INVPCID (1U << 10)
> +/* Restricted Transactional Memory */
> +#define CPUID_7_0_EBX_RTM (1U << 11)
> +/* Memory Protection Extension */
> +#define CPUID_7_0_EBX_MPX (1U << 14)
> +/* AVX-512 Foundation */
> +#define CPUID_7_0_EBX_AVX512F (1U << 16)
> +/* AVX-512 Doubleword & Quadword Instruction */
> +#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
> +/* Read Random SEED */
> +#define CPUID_7_0_EBX_RDSEED (1U << 18)
> +/* ADCX and ADOX instructions */
> +#define CPUID_7_0_EBX_ADX (1U << 19)
> +/* Supervisor Mode Access Prevention */
> +#define CPUID_7_0_EBX_SMAP (1U << 20)
> +/* AVX-512 Integer Fused Multiply Add */
> +#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
> +/* Persistent Commit */
> +#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
> +/* Flush a Cache Line Optimized */
> +#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
> +/* Cache Line Write Back */
> +#define CPUID_7_0_EBX_CLWB (1U << 24)
> +/* Intel Processor Trace */
> +#define CPUID_7_0_EBX_INTEL_PT (1U << 25)
> +/* AVX-512 Prefetch */
> +#define CPUID_7_0_EBX_AVX512PF (1U << 26)
> +/* AVX-512 Exponential and Reciprocal */
> +#define CPUID_7_0_EBX_AVX512ER (1U << 27)
> +/* AVX-512 Conflict Detection */
> +#define CPUID_7_0_EBX_AVX512CD (1U << 28)
> +/* SHA1/SHA256 Instruction Extensions */
> +#define CPUID_7_0_EBX_SHA_NI (1U << 29)
> +/* AVX-512 Byte and Word Instructions */
> +#define CPUID_7_0_EBX_AVX512BW (1U << 30)
> +/* AVX-512 Vector Length Extensions */
> +#define CPUID_7_0_EBX_AVX512VL (1U << 31)
> +
> +/* AVX-512 Vector Byte Manipulation Instruction */
> +#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
> +#define CPUID_7_0_ECX_VBMI (1U << 1)
> +/* User-Mode Instruction Prevention */
> +#define CPUID_7_0_ECX_UMIP (1U << 2)
> +/* Protection Keys for User-mode Pages */
> +#define CPUID_7_0_ECX_PKU (1U << 3)
> +/* OS Enable Protection Keys */
> +#define CPUID_7_0_ECX_OSPKE (1U << 4)
> +/* Additional AVX-512 Vector Byte Manipulation Instruction */
> +#define CPUID_7_0_ECX_VBMI2 (1U << 6)
> +/* Galois Field New Instructions */
> +#define CPUID_7_0_ECX_GFNI (1U << 8)
> +/* Vector AES Instructions */
> +#define CPUID_7_0_ECX_VAES (1U << 9)
> +/* Carry-Less Multiplication Quadword */
> +#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
> +/* Vector Neural Network Instructions */
> +#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
> +/* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
> +#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
> +/* POPCNT for vectors of DW/QW */
> +#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
> +/* 5-level Page Tables */
> +#define CPUID_7_0_ECX_LA57 (1U << 16)
> +/* Read Processor ID */
> +#define CPUID_7_0_ECX_RDPID (1U << 22)
> +/* Cache Line Demote Instruction */
> +#define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
> +/* Move Doubleword as Direct Store Instruction */
> +#define CPUID_7_0_ECX_MOVDIRI (1U << 27)
> +/* Move 64 Bytes as Direct Store Instruction */
> +#define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
> +
> +/* AVX512 Neural Network Instructions */
> +#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
> +/* AVX512 Multiply Accumulation Single Precision */
> +#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
> +/* Speculation Control */
> +#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
> +/* Arch Capabilities */
> +#define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
> +/* Core Capability */
> +#define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
> +/* Speculative Store Bypass Disable */
> +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
> +
> +/* AVX512 BFloat16 Instruction */
> +#define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
> +
> +/* Write back and do not invalidate cache */
> +#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
> +/* Indirect Branch Prediction Barrier */
> +#define CPUID_8000_0008_EBX_IBPB (1U << 12)
>
> #define CPUID_XSAVE_XSAVEOPT (1U << 0)
> #define CPUID_XSAVE_XSAVEC (1U << 1)
> --
> 2.20.1
>
--
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco
2019-09-23 6:30 [PATCH v3 0/2] target/i386: cpu.h marcos clean up Tao Xu
2019-09-23 6:30 ` [PATCH v3 1/2] target/i386: clean up comments over 80 chars per line Tao Xu
@ 2019-09-23 6:30 ` Tao Xu
2019-09-23 8:08 ` Stefano Garzarella
1 sibling, 1 reply; 6+ messages in thread
From: Tao Xu @ 2019-09-23 6:30 UTC (permalink / raw)
To: ehabkost, sgarzare, philmd, pbonzini, rth; +Cc: Tao Xu, qemu-devel
Drop the duplicated definition of cpuid AVX512_VBMI marco and rename it
as CPUID_7_0_ECX_AVX512_VBMI.
Signed-off-by: Tao Xu <tao3.xu@intel.com>
---
target/i386/cpu.c | 4 ++--
target/i386/cpu.h | 3 +--
target/i386/hvf/x86_cpuid.c | 2 +-
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 9e0bac31e8..f87fe88259 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2412,7 +2412,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
.features[FEAT_7_0_ECX] =
- CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
+ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
@@ -2470,7 +2470,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
.features[FEAT_7_0_ECX] =
- CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
+ CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index fa4c4cad79..61f6287294 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -695,8 +695,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_AVX512VL (1U << 31)
/* AVX-512 Vector Byte Manipulation Instruction */
-#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
-#define CPUID_7_0_ECX_VBMI (1U << 1)
+#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
/* User-Mode Instruction Prevention */
#define CPUID_7_0_ECX_UMIP (1U << 2)
/* Protection Keys for User-mode Pages */
diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c
index 4d957fe896..16762b6eb4 100644
--- a/target/i386/hvf/x86_cpuid.c
+++ b/target/i386/hvf/x86_cpuid.c
@@ -89,7 +89,7 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
ebx &= ~CPUID_7_0_EBX_INVPCID;
}
- ecx &= CPUID_7_0_ECX_AVX512BMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;
+ ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;
edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;
} else {
ebx = 0;
--
2.20.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco
2019-09-23 6:30 ` [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco Tao Xu
@ 2019-09-23 8:08 ` Stefano Garzarella
2019-09-23 8:35 ` Tao Xu
0 siblings, 1 reply; 6+ messages in thread
From: Stefano Garzarella @ 2019-09-23 8:08 UTC (permalink / raw)
To: Tao Xu; +Cc: qemu-devel, pbonzini, philmd, ehabkost, rth
On Mon, Sep 23, 2019 at 02:30:41PM +0800, Tao Xu wrote:
> Drop the duplicated definition of cpuid AVX512_VBMI marco and rename it
> as CPUID_7_0_ECX_AVX512_VBMI.
>
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> ---
> target/i386/cpu.c | 4 ++--
> target/i386/cpu.h | 3 +--
> target/i386/hvf/x86_cpuid.c | 2 +-
> 3 files changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 9e0bac31e8..f87fe88259 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -2412,7 +2412,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
> CPUID_7_0_EBX_SMAP,
> .features[FEAT_7_0_ECX] =
> - CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
> CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> @@ -2470,7 +2470,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
> CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
> .features[FEAT_7_0_ECX] =
> - CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
> CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
> CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
> CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index fa4c4cad79..61f6287294 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -695,8 +695,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_EBX_AVX512VL (1U << 31)
>
> /* AVX-512 Vector Byte Manipulation Instruction */
> -#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
> -#define CPUID_7_0_ECX_VBMI (1U << 1)
> +#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
Since we're here, should we also update CPUID_7_0_ECX_VBMI2?
Thanks,
Stefano
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco
2019-09-23 8:08 ` Stefano Garzarella
@ 2019-09-23 8:35 ` Tao Xu
0 siblings, 0 replies; 6+ messages in thread
From: Tao Xu @ 2019-09-23 8:35 UTC (permalink / raw)
To: Stefano Garzarella; +Cc: qemu-devel, pbonzini, philmd, ehabkost, rth
On 9/23/2019 4:08 PM, Stefano Garzarella wrote:
> On Mon, Sep 23, 2019 at 02:30:41PM +0800, Tao Xu wrote:
>> Drop the duplicated definition of cpuid AVX512_VBMI marco and rename it
>> as CPUID_7_0_ECX_AVX512_VBMI.
>>
>> Signed-off-by: Tao Xu <tao3.xu@intel.com>
>> ---
>> target/i386/cpu.c | 4 ++--
>> target/i386/cpu.h | 3 +--
>> target/i386/hvf/x86_cpuid.c | 2 +-
>> 3 files changed, 4 insertions(+), 5 deletions(-)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 9e0bac31e8..f87fe88259 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -2412,7 +2412,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>> CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
>> CPUID_7_0_EBX_SMAP,
>> .features[FEAT_7_0_ECX] =
>> - CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
>> + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
>> CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
>> CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
>> CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
>> @@ -2470,7 +2470,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>> CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
>> CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
>> .features[FEAT_7_0_ECX] =
>> - CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
>> + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
>> CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
>> CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
>> CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
>> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
>> index fa4c4cad79..61f6287294 100644
>> --- a/target/i386/cpu.h
>> +++ b/target/i386/cpu.h
>> @@ -695,8 +695,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>> #define CPUID_7_0_EBX_AVX512VL (1U << 31)
>>
>> /* AVX-512 Vector Byte Manipulation Instruction */
>> -#define CPUID_7_0_ECX_AVX512BMI (1U << 1)
>> -#define CPUID_7_0_ECX_VBMI (1U << 1)
>> +#define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
>
> Since we're here, should we also update CPUID_7_0_ECX_VBMI2?
>
> Thanks,
> Stefano
>
Thank you for reminding me. I check the vmbi2's flag is 'avx512_vbmi2'.
And linux kernel source and SDM also use AVX512_VBMI2. I will update this.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-09-23 8:59 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2019-09-23 6:30 [PATCH v3 0/2] target/i386: cpu.h marcos clean up Tao Xu
2019-09-23 6:30 ` [PATCH v3 1/2] target/i386: clean up comments over 80 chars per line Tao Xu
2019-09-23 8:06 ` Stefano Garzarella
2019-09-23 6:30 ` [PATCH v3 2/2] target/i386: drop the duplicated definition of cpuid AVX512_VBMI marco Tao Xu
2019-09-23 8:08 ` Stefano Garzarella
2019-09-23 8:35 ` Tao Xu
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