From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
"Cédric Le Goater" <clg@kaod.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org,
"Joel Stanley" <joel@jms.id.au>
Subject: [PATCH v2 12/23] aspeed/smc: Introduce segment operations
Date: Wed, 25 Sep 2019 16:32:37 +0200 [thread overview]
Message-ID: <20190925143248.10000-13-clg@kaod.org> (raw)
In-Reply-To: <20190925143248.10000-1-clg@kaod.org>
AST2600 will use a different encoding for the addresses defined in the
Segment Register.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ssi/aspeed_smc.h | 4 ++++
hw/ssi/aspeed_smc.c | 45 ++++++++++++++++++++++++-------------
2 files changed, 34 insertions(+), 15 deletions(-)
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index 5176ff6bf95f..684d16e33613 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -49,6 +49,10 @@ typedef struct AspeedSMCController {
hwaddr dma_flash_mask;
hwaddr dma_dram_mask;
uint32_t nregs;
+ uint32_t (*segment_to_reg)(const struct AspeedSMCState *s,
+ const AspeedSegments *seg);
+ void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg,
+ AspeedSegments *seg);
} AspeedSMCController;
typedef struct AspeedSMCFlash {
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 9ffc7e01179a..9909135a2cfe 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -211,6 +211,10 @@ static const AspeedSegments aspeed_segments_ast2500_spi2[] = {
{ 0x38000000, 32 * 1024 * 1024 }, /* start address is readonly */
{ 0x3A000000, 96 * 1024 * 1024 }, /* end address is readonly */
};
+static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
+ const AspeedSegments *seg);
+static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg,
+ AspeedSegments *seg);
static const AspeedSMCController controllers[] = {
{
@@ -226,6 +230,8 @@ static const AspeedSMCController controllers[] = {
.flash_window_size = 0x6000000,
.has_dma = false,
.nregs = ASPEED_SMC_R_SMC_MAX,
+ .segment_to_reg = aspeed_smc_segment_to_reg,
+ .reg_to_segment = aspeed_smc_reg_to_segment,
}, {
.name = "aspeed.fmc-ast2400",
.r_conf = R_CONF,
@@ -241,6 +247,8 @@ static const AspeedSMCController controllers[] = {
.dma_flash_mask = 0x0FFFFFFC,
.dma_dram_mask = 0x1FFFFFFC,
.nregs = ASPEED_SMC_R_MAX,
+ .segment_to_reg = aspeed_smc_segment_to_reg,
+ .reg_to_segment = aspeed_smc_reg_to_segment,
}, {
.name = "aspeed.spi1-ast2400",
.r_conf = R_SPI_CONF,
@@ -254,6 +262,8 @@ static const AspeedSMCController controllers[] = {
.flash_window_size = 0x10000000,
.has_dma = false,
.nregs = ASPEED_SMC_R_SPI_MAX,
+ .segment_to_reg = aspeed_smc_segment_to_reg,
+ .reg_to_segment = aspeed_smc_reg_to_segment,
}, {
.name = "aspeed.fmc-ast2500",
.r_conf = R_CONF,
@@ -269,6 +279,8 @@ static const AspeedSMCController controllers[] = {
.dma_flash_mask = 0x0FFFFFFC,
.dma_dram_mask = 0x3FFFFFFC,
.nregs = ASPEED_SMC_R_MAX,
+ .segment_to_reg = aspeed_smc_segment_to_reg,
+ .reg_to_segment = aspeed_smc_reg_to_segment,
}, {
.name = "aspeed.spi1-ast2500",
.r_conf = R_CONF,
@@ -282,6 +294,8 @@ static const AspeedSMCController controllers[] = {
.flash_window_size = 0x8000000,
.has_dma = false,
.nregs = ASPEED_SMC_R_MAX,
+ .segment_to_reg = aspeed_smc_segment_to_reg,
+ .reg_to_segment = aspeed_smc_reg_to_segment,
}, {
.name = "aspeed.spi2-ast2500",
.r_conf = R_CONF,
@@ -295,19 +309,19 @@ static const AspeedSMCController controllers[] = {
.flash_window_size = 0x8000000,
.has_dma = false,
.nregs = ASPEED_SMC_R_MAX,
+ .segment_to_reg = aspeed_smc_segment_to_reg,
+ .reg_to_segment = aspeed_smc_reg_to_segment,
},
};
/*
- * The Segment Register uses a 8MB unit to encode the start address
- * and the end address of the mapping window of a flash SPI slave :
- *
- * | byte 1 | byte 2 | byte 3 | byte 4 |
- * +--------+--------+--------+--------+
- * | end | start | 0 | 0 |
- *
+ * The Segment Registers of the AST2400 and AST2500 have a 8MB
+ * unit. The address range of a flash SPI slave is encoded with
+ * absolute addresses which should be part of the overall controller
+ * window.
*/
-static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg)
+static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s,
+ const AspeedSegments *seg)
{
uint32_t reg = 0;
reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT;
@@ -315,7 +329,8 @@ static inline uint32_t aspeed_smc_segment_to_reg(const AspeedSegments *seg)
return reg;
}
-static inline void aspeed_smc_reg_to_segment(uint32_t reg, AspeedSegments *seg)
+static void aspeed_smc_reg_to_segment(const AspeedSMCState *s,
+ uint32_t reg, AspeedSegments *seg)
{
seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23;
seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr;
@@ -333,7 +348,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
continue;
}
- aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + i], &seg);
+ s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg);
if (new->addr + new->size > seg.addr &&
new->addr < seg.addr + seg.size) {
@@ -354,7 +369,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
AspeedSMCFlash *fl = &s->flashes[cs];
AspeedSegments seg;
- aspeed_smc_reg_to_segment(new, &seg);
+ s->ctrl->reg_to_segment(s, new, &seg);
/* The start address of CS0 is read-only */
if (cs == 0 && seg.addr != s->ctrl->flash_window_base) {
@@ -362,7 +377,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
"%s: Tried to change CS0 start address to 0x%"
HWADDR_PRIx "\n", s->ctrl->name, seg.addr);
seg.addr = s->ctrl->flash_window_base;
- new = aspeed_smc_segment_to_reg(&seg);
+ new = s->ctrl->segment_to_reg(s, &seg);
}
/*
@@ -379,7 +394,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
HWADDR_PRIx "\n", s->ctrl->name, cs, seg.addr + seg.size);
seg.size = s->ctrl->segments[cs].addr + s->ctrl->segments[cs].size -
seg.addr;
- new = aspeed_smc_segment_to_reg(&seg);
+ new = s->ctrl->segment_to_reg(s, &seg);
}
/* Keep the segment in the overall flash window */
@@ -509,7 +524,7 @@ static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
const AspeedSMCState *s = fl->controller;
AspeedSegments seg;
- aspeed_smc_reg_to_segment(s->regs[R_SEG_ADDR0 + fl->id], &seg);
+ s->ctrl->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->id], &seg);
if ((addr % seg.size) != addr) {
qemu_log_mask(LOG_GUEST_ERROR,
"%s: invalid address 0x%08x for CS%d segment : "
@@ -769,7 +784,7 @@ static void aspeed_smc_reset(DeviceState *d)
/* setup default segment register values for all */
for (i = 0; i < s->ctrl->max_slaves; ++i) {
s->regs[R_SEG_ADDR0 + i] =
- aspeed_smc_segment_to_reg(&s->ctrl->segments[i]);
+ s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]);
}
/* HW strapping flash type for FMC controllers */
--
2.21.0
next prev parent reply other threads:[~2019-09-25 14:55 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-25 14:32 [PATCH v2 00/23] aspeed: Add support for the AST2600 SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 01/23] aspeed/wdt: Check correct register for clock source Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 02/23] hw/sd/aspeed_sdhci: New device Cédric Le Goater
2019-09-26 8:27 ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 03/23] hw: aspeed_scu: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 04/23] aspeed/timer: Introduce an object class per SoC Cédric Le Goater
2019-09-26 8:29 ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 05/23] aspeed/timer: Add support for control register 3 Cédric Le Goater
2019-09-26 8:30 ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 06/23] aspeed/timer: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 07/23] aspeed/timer: Add support for IRQ status register on the AST2600 Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 08/23] aspeed/sdmc: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 09/23] aspeed/sdmc: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 10/23] watchdog/aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 11/23] hw: wdt_aspeed: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` Cédric Le Goater [this message]
2019-09-26 8:23 ` [PATCH v2 12/23] aspeed/smc: Introduce segment operations Joel Stanley
2019-09-25 14:32 ` [PATCH v2 13/23] aspeed/smc: Add AST2600 support Cédric Le Goater
2019-09-26 8:24 ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 14/23] hw/gpio: Add in AST2600 specific implementation Cédric Le Goater
2019-09-26 8:24 ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 15/23] aspeed/i2c: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 16/23] aspeed/i2c: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 17/23] aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 18/23] aspeed/soc: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 19/23] m25p80: Add support for w25q512jv Cédric Le Goater
2019-09-26 8:25 ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 20/23] aspeed: Add an AST2600 eval board Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 21/23] aspeed: Parameterise number of MACs Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 22/23] aspeed: add support for the Aspeed MII controller of the AST2600 Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 23/23] aspeed/soc: Add ASPEED Video stub Cédric Le Goater
2019-10-14 15:46 ` [PATCH v2 00/23] aspeed: Add support for the AST2600 SoC Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190925143248.10000-13-clg@kaod.org \
--to=clg@kaod.org \
--cc=andrew@aj.id.au \
--cc=joel@jms.id.au \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).