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From: "Cédric Le Goater" <clg@kaod.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Andrew Jeffery" <andrew@aj.id.au>,
	"Cédric Le Goater" <clg@kaod.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org,
	"Joel Stanley" <joel@jms.id.au>
Subject: [PATCH v2 21/23] aspeed: Parameterise number of MACs
Date: Wed, 25 Sep 2019 16:32:46 +0200	[thread overview]
Message-ID: <20190925143248.10000-22-clg@kaod.org> (raw)
In-Reply-To: <20190925143248.10000-1-clg@kaod.org>

From: Joel Stanley <joel@jms.id.au>

To support the ast2600's four MACs allow SoCs to specify the number
they have, and create that many.

Signed-off-by: Joel Stanley <joel@jms.id.au>
[clg: - included a check on sc->macs_num when realizing the macs
      - included interrupt definitions for the AST2600 ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 include/hw/arm/aspeed_soc.h |  5 ++++-
 hw/arm/aspeed_ast2600.c     | 10 ++++++++--
 hw/arm/aspeed_soc.c         |  6 ++++--
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 67c59956f835..088a5d108185 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -30,7 +30,7 @@
 #define ASPEED_SPIS_NUM  2
 #define ASPEED_WDTS_NUM  4
 #define ASPEED_CPUS_NUM  2
-#define ASPEED_MACS_NUM  2
+#define ASPEED_MACS_NUM  4
 
 typedef struct AspeedSoCState {
     /*< private >*/
@@ -69,6 +69,7 @@ typedef struct AspeedSoCClass {
     uint64_t sram_size;
     int spis_num;
     int wdts_num;
+    int macs_num;
     const int *irqmap;
     const hwaddr *memmap;
     uint32_t num_cpus;
@@ -114,6 +115,8 @@ enum {
     ASPEED_I2C,
     ASPEED_ETH1,
     ASPEED_ETH2,
+    ASPEED_ETH3,
+    ASPEED_ETH4,
     ASPEED_SDRAM,
     ASPEED_XDMA,
 };
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index a4f0fafab7cb..25d2c2d05d63 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -32,7 +32,9 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
     [ASPEED_SPI1]      = 0x1E630000,
     [ASPEED_SPI2]      = 0x1E641000,
     [ASPEED_ETH1]      = 0x1E660000,
+    [ASPEED_ETH3]      = 0x1E670000,
     [ASPEED_ETH2]      = 0x1E680000,
+    [ASPEED_ETH4]      = 0x1E690000,
     [ASPEED_VIC]       = 0x1E6C0000,
     [ASPEED_SDMC]      = 0x1E6E0000,
     [ASPEED_SCU]       = 0x1E6E2000,
@@ -88,6 +90,9 @@ static const int aspeed_soc_ast2600_irqmap[] = {
     [ASPEED_I2C]       = 110,   /* 110 -> 125 */
     [ASPEED_ETH1]      = 2,
     [ASPEED_ETH2]      = 3,
+    [ASPEED_ETH3]      = 32,
+    [ASPEED_ETH4]      = 33,
+
 };
 
 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
@@ -173,7 +178,7 @@ static void aspeed_soc_ast2600_init(Object *obj)
                                        OBJECT(&s->scu), &error_abort);
     }
 
-    for (i = 0; i < ASPEED_MACS_NUM; i++) {
+    for (i = 0; i < sc->macs_num; i++) {
         sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
                               sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
     }
@@ -397,7 +402,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
     }
 
     /* Net */
-    for (i = 0; i < nb_nics; i++) {
+    for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
         qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
         object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
                                  &err);
@@ -470,6 +475,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
     sc->sram_size    = 0x10000;
     sc->spis_num     = 2;
     sc->wdts_num     = 4;
+    sc->macs_num     = 4;
     sc->irqmap       = aspeed_soc_ast2600_irqmap;
     sc->memmap       = aspeed_soc_ast2600_memmap;
     sc->num_cpus     = 2;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index a063be9fd795..6defb143acde 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -198,7 +198,7 @@ static void aspeed_soc_init(Object *obj)
                                        OBJECT(&s->scu), &error_abort);
     }
 
-    for (i = 0; i < ASPEED_MACS_NUM; i++) {
+    for (i = 0; i < sc->macs_num; i++) {
         sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
                               sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
     }
@@ -372,7 +372,7 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
     }
 
     /* Net */
-    for (i = 0; i < nb_nics; i++) {
+    for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
         qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
         object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
                                  &err);
@@ -455,6 +455,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
     sc->sram_size    = 0x8000;
     sc->spis_num     = 1;
     sc->wdts_num     = 2;
+    sc->macs_num     = 2;
     sc->irqmap       = aspeed_soc_ast2400_irqmap;
     sc->memmap       = aspeed_soc_ast2400_memmap;
     sc->num_cpus     = 1;
@@ -478,6 +479,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
     sc->sram_size    = 0x9000;
     sc->spis_num     = 2;
     sc->wdts_num     = 3;
+    sc->macs_num     = 2;
     sc->irqmap       = aspeed_soc_ast2500_irqmap;
     sc->memmap       = aspeed_soc_ast2500_memmap;
     sc->num_cpus     = 1;
-- 
2.21.0



  parent reply	other threads:[~2019-09-25 14:56 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-25 14:32 [PATCH v2 00/23] aspeed: Add support for the AST2600 SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 01/23] aspeed/wdt: Check correct register for clock source Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 02/23] hw/sd/aspeed_sdhci: New device Cédric Le Goater
2019-09-26  8:27   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 03/23] hw: aspeed_scu: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 04/23] aspeed/timer: Introduce an object class per SoC Cédric Le Goater
2019-09-26  8:29   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 05/23] aspeed/timer: Add support for control register 3 Cédric Le Goater
2019-09-26  8:30   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 06/23] aspeed/timer: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 07/23] aspeed/timer: Add support for IRQ status register on the AST2600 Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 08/23] aspeed/sdmc: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 09/23] aspeed/sdmc: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 10/23] watchdog/aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 11/23] hw: wdt_aspeed: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 12/23] aspeed/smc: Introduce segment operations Cédric Le Goater
2019-09-26  8:23   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 13/23] aspeed/smc: Add AST2600 support Cédric Le Goater
2019-09-26  8:24   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 14/23] hw/gpio: Add in AST2600 specific implementation Cédric Le Goater
2019-09-26  8:24   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 15/23] aspeed/i2c: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 16/23] aspeed/i2c: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 17/23] aspeed: Introduce an object class per SoC Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 18/23] aspeed/soc: Add AST2600 support Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 19/23] m25p80: Add support for w25q512jv Cédric Le Goater
2019-09-26  8:25   ` Joel Stanley
2019-09-25 14:32 ` [PATCH v2 20/23] aspeed: Add an AST2600 eval board Cédric Le Goater
2019-09-25 14:32 ` Cédric Le Goater [this message]
2019-09-25 14:32 ` [PATCH v2 22/23] aspeed: add support for the Aspeed MII controller of the AST2600 Cédric Le Goater
2019-09-25 14:32 ` [PATCH v2 23/23] aspeed/soc: Add ASPEED Video stub Cédric Le Goater
2019-10-14 15:46 ` [PATCH v2 00/23] aspeed: Add support for the AST2600 SoC Peter Maydell

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