* [PATCH] intel_iommu: TM field should not be in reserved bits
@ 2019-09-26 5:49 qi1.zhang
2019-09-26 8:47 ` Michael S. Tsirkin
0 siblings, 1 reply; 2+ messages in thread
From: qi1.zhang @ 2019-09-26 5:49 UTC (permalink / raw)
To: qemu-devel; +Cc: qi1.zhang, ehabkost, mst, pbonzini, rth
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..2696ceeb9d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3567,6 +3567,13 @@ static void vtd_init(IntelIOMMUState *s)
if (x86_iommu->dt_supported) {
s->ecap |= VTD_ECAP_DT;
+ vtd_paging_entry_rsvd_field[1] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[2] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[3] &= ~(1ULL << 62);
+
+ vtd_paging_entry_rsvd_field[5] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[6] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[7] &= ~(1ULL << 62);
}
if (x86_iommu->pt_supported) {
--
2.20.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] intel_iommu: TM field should not be in reserved bits
2019-09-26 5:49 [PATCH] intel_iommu: TM field should not be in reserved bits qi1.zhang
@ 2019-09-26 8:47 ` Michael S. Tsirkin
0 siblings, 0 replies; 2+ messages in thread
From: Michael S. Tsirkin @ 2019-09-26 8:47 UTC (permalink / raw)
To: qi1.zhang; +Cc: pbonzini, ehabkost, qemu-devel, rth
On Thu, Sep 26, 2019 at 01:49:22PM +0800, qi1.zhang@intel.com wrote:
> From: "Zhang, Qi" <qi1.zhang@intel.com>
>
> When dt is supported, TM field should not be Reserved(0).
>
> Refer to VT-d Spec 9.8
>
> Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
> Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
> ---
> hw/i386/intel_iommu.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index f1de8fdb75..2696ceeb9d 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3567,6 +3567,13 @@ static void vtd_init(IntelIOMMUState *s)
>
> if (x86_iommu->dt_supported) {
> s->ecap |= VTD_ECAP_DT;
> + vtd_paging_entry_rsvd_field[1] &= ~(1ULL << 62);
> + vtd_paging_entry_rsvd_field[2] &= ~(1ULL << 62);
> + vtd_paging_entry_rsvd_field[3] &= ~(1ULL << 62);
> +
> + vtd_paging_entry_rsvd_field[5] &= ~(1ULL << 62);
> + vtd_paging_entry_rsvd_field[6] &= ~(1ULL << 62);
> + vtd_paging_entry_rsvd_field[7] &= ~(1ULL << 62);
Add a macro for this value, please.
And I think it's cleaner to pass dt_supported flag
to VTD_SPTE_PAGE_LX_RSVD_MASK and VTD_SPTE_LPAGE_LX_RSVD_MASK,
rather than set bits then clear them selectively.
> }
>
> if (x86_iommu->pt_supported) {
> --
> 2.20.1
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2019-09-26 16:37 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-09-26 5:49 [PATCH] intel_iommu: TM field should not be in reserved bits qi1.zhang
2019-09-26 8:47 ` Michael S. Tsirkin
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).