From: qi1.zhang@intel.com
To: qemu-devel@nongnu.org
Cc: qi1.zhang@intel.com, ehabkost@redhat.com, mst@redhat.com,
pbonzini@redhat.com, rth@twiddle.net
Subject: [PATCH] intel_iommu: TM field should not be in reserved bits
Date: Thu, 26 Sep 2019 13:49:22 +0800 [thread overview]
Message-ID: <20190926054922.21110-1-qi1.zhang@intel.com> (raw)
From: "Zhang, Qi" <qi1.zhang@intel.com>
When dt is supported, TM field should not be Reserved(0).
Refer to VT-d Spec 9.8
Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
---
hw/i386/intel_iommu.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f1de8fdb75..2696ceeb9d 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -3567,6 +3567,13 @@ static void vtd_init(IntelIOMMUState *s)
if (x86_iommu->dt_supported) {
s->ecap |= VTD_ECAP_DT;
+ vtd_paging_entry_rsvd_field[1] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[2] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[3] &= ~(1ULL << 62);
+
+ vtd_paging_entry_rsvd_field[5] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[6] &= ~(1ULL << 62);
+ vtd_paging_entry_rsvd_field[7] &= ~(1ULL << 62);
}
if (x86_iommu->pt_supported) {
--
2.20.1
next reply other threads:[~2019-09-26 16:37 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 5:49 qi1.zhang [this message]
2019-09-26 8:47 ` [PATCH] intel_iommu: TM field should not be in reserved bits Michael S. Tsirkin
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