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Fri, 27 Sep 2019 02:32:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyz3UiS5nvzuqeXSjJLmzd6fvm7V8YIpGiFRgwCXq9rx7oE8mStrFQV/OYbUISEQGV2S24AaA== X-Received: by 2002:a17:90a:2086:: with SMTP id f6mr8816410pjg.104.1569576753307; Fri, 27 Sep 2019 02:32:33 -0700 (PDT) Received: from xz-x1 ([209.132.188.80]) by smtp.gmail.com with ESMTPSA id b5sm4182873pgb.68.2019.09.27.02.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2019 02:32:32 -0700 (PDT) Date: Fri, 27 Sep 2019 17:32:23 +0800 From: Peter Xu To: "Zhang, Qi1" Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits Message-ID: <20190927093223.GC9412@xz-x1> References: <20190927045838.2968-1-qi1.zhang@intel.com> <20190927061011.GB9412@xz-x1> <215440059103624D9AD9D1DCACBF45DD3E84E270@shsmsx102.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <215440059103624D9AD9D1DCACBF45DD3E84E270@shsmsx102.ccr.corp.intel.com> User-Agent: Mutt/1.11.4 (2019-03-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ehabkost@redhat.com" , "mst@redhat.com" , "qemu-devel@nongnu.org" , "pbonzini@redhat.com" , "Qi, Yadong" , "rth@twiddle.net" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Sep 27, 2019 at 08:03:21AM +0000, Zhang, Qi1 wrote: > > > > -----Original Message----- > > From: Peter Xu > > Sent: Friday, September 27, 2019 2:10 PM > > To: Zhang, Qi1 > > Cc: qemu-devel@nongnu.org; ehabkost@redhat.com; mst@redhat.com; > > pbonzini@redhat.com; rth@twiddle.net > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits > > > > On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zhang@intel.com wrote: > > > From: "Zhang, Qi" > > > > > > When dt is supported, TM field should not be Reserved(0). > > > > > > Refer to VT-d Spec 9.8 > > > > > > Signed-off-by: Zhang, Qi > > > Signed-off-by: Qi, Yadong > > > --- > > > hw/i386/intel_iommu.c | 12 ++++++------ > > > hw/i386/intel_iommu_internal.h | 25 +++++++++++++++++++------ > > > 2 files changed, 25 insertions(+), 12 deletions(-) > > > --- > > > Changelog V2: > > > move dt_supported flag to VTD_SPTE_PAGE_LX_RSVD_MASK and > > > VTD_SPTE_LPAGE_LX_RSVD_MASK > > > > > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index > > > f1de8fdb75..35222cf55c 100644 > > > --- a/hw/i386/intel_iommu.c > > > +++ b/hw/i386/intel_iommu.c > > > @@ -3548,13 +3548,13 @@ static void vtd_init(IntelIOMMUState *s) > > > * Rsvd field masks for spte > > > */ > > > vtd_paging_entry_rsvd_field[0] = ~0ULL; > > > - vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s- > > >aw_bits); > > > - vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s- > > >aw_bits); > > > - vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s- > > >aw_bits); > > > + vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s- > > >aw_bits, x86_iommu->dt_supported); > > > + vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s- > > >aw_bits, x86_iommu->dt_supported); > > > + vtd_paging_entry_rsvd_field[3] = > > > + VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu- > > >dt_supported); > > > vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s- > > >aw_bits); > > > - vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s- > > >aw_bits); > > > - vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s- > > >aw_bits); > > > - vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s- > > >aw_bits); > > > + vtd_paging_entry_rsvd_field[5] = > > VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, x86_iommu- > > >dt_supported); > > > + vtd_paging_entry_rsvd_field[6] = > > VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, x86_iommu- > > >dt_supported); > > > + vtd_paging_entry_rsvd_field[7] = > > > + VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu- > > >dt_supported); > > > vtd_paging_entry_rsvd_field[8] = > > > VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); > > > > Should this TM bit only affects leaves? Say, entry 1 (4K), 5 (2M), 6 (1G). > > While this reminded me that I'm totally confused on why we have had entry > > 7, 8 after all... Are they really used? > Yes. TM bit only affects. To this array, index 1, 5,6,7 may be leaf. Will update a new patchset for it. Could I ask why index 7 may be leaf? > > > > > > > > if (x86_iommu_ir_supported(x86_iommu)) { diff --git > > > a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > > > index c1235a7063..01f1aa6c86 100644 > > > --- a/hw/i386/intel_iommu_internal.h > > > +++ b/hw/i386/intel_iommu_internal.h > > > @@ -387,19 +387,31 @@ typedef union VTDInvDesc VTDInvDesc; #define > > > VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 > > > > > > /* Rsvd field masks for spte */ > > > -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ > > > +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ > > > + dt_supported? \ > > > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | > > VTD_SL_TM)) > > > +: \ > > > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > > > > This seems strange too in that ~VTD_HAW_MASK(aw) probably covered bits > > 63-48 for aw==48 case so it should already cover VTD_SL_TM? > VTD_SL_IGN_COM 0xbff0000000000000ULL, TM field is cleared by ~ VTD_SL_IGN_COM > > > > Meanwhile when I'm reading the spec I see at least bits 61-52 ignored rather > > than reserved. > Yes. Bit 61~52 is ignored. Such as the index 5 of this array is 0xfff8000000800. Oops, my poor eye obviously didn't see that the "~" operator is applied over the whole (VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)... :) Btw, you should only touch up the macros that are leaves here. Non-leaves should still keep that bit as reserved. Thanks, -- Peter Xu