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Sat, 28 Sep 2019 19:02:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwLFu+5EEyOJ5Y3ags50JTZ884D1jHZedtlhSp5Trc9pGTVJSTQjQ3o4ULO0JJDsWoEM8wig== X-Received: by 2002:a17:90a:c096:: with SMTP id o22mr19396710pjs.29.1569722550855; Sat, 28 Sep 2019 19:02:30 -0700 (PDT) Received: from xz-x1 ([209.132.188.80]) by smtp.gmail.com with ESMTPSA id s73sm9262267pjb.15.2019.09.28.19.02.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Sep 2019 19:02:29 -0700 (PDT) Date: Sun, 29 Sep 2019 10:02:20 +0800 From: Peter Xu To: "Zhang, Qi1" Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits Message-ID: <20190929020220.GA8286@xz-x1> References: <20190927045838.2968-1-qi1.zhang@intel.com> <20190927061011.GB9412@xz-x1> <215440059103624D9AD9D1DCACBF45DD3E84E270@shsmsx102.ccr.corp.intel.com> <20190927093223.GC9412@xz-x1> <215440059103624D9AD9D1DCACBF45DD3E853A42@shsmsx102.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <215440059103624D9AD9D1DCACBF45DD3E853A42@shsmsx102.ccr.corp.intel.com> User-Agent: Mutt/1.11.4 (2019-03-13) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "ehabkost@redhat.com" , "mst@redhat.com" , "qemu-devel@nongnu.org" , "pbonzini@redhat.com" , "Qi, Yadong" , "rth@twiddle.net" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Sun, Sep 29, 2019 at 01:11:12AM +0000, Zhang, Qi1 wrote: > > > > -----Original Message----- > > From: Peter Xu > > Sent: Friday, September 27, 2019 5:32 PM > > To: Zhang, Qi1 > > Cc: qemu-devel@nongnu.org; ehabkost@redhat.com; mst@redhat.com; > > pbonzini@redhat.com; rth@twiddle.net; Qi, Yadong > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits > > > > On Fri, Sep 27, 2019 at 08:03:21AM +0000, Zhang, Qi1 wrote: > > > > > > > > > > -----Original Message----- > > > > From: Peter Xu > > > > Sent: Friday, September 27, 2019 2:10 PM > > > > To: Zhang, Qi1 > > > > Cc: qemu-devel@nongnu.org; ehabkost@redhat.com; mst@redhat.com; > > > > pbonzini@redhat.com; rth@twiddle.net > > > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in > > > > reserved bits > > > > > > > > On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zhang@intel.com wrote: > > > > > From: "Zhang, Qi" > > > > > > > > > > When dt is supported, TM field should not be Reserved(0). > > > > > > > > > > Refer to VT-d Spec 9.8 > > > > > > > > > > Signed-off-by: Zhang, Qi > > > > > Signed-off-by: Qi, Yadong > > > > > --- > > > > > hw/i386/intel_iommu.c | 12 ++++++------ > > > > > hw/i386/intel_iommu_internal.h | 25 +++++++++++++++++++------ > > > > > 2 files changed, 25 insertions(+), 12 deletions(-) > > > > > --- > > VTD_SPTE_PAGE_L2_RSVD_MASK(s- > > > > >aw_bits); > > > > > - vtd_paging_entry_rsvd_field[3] = > > > > >aw_bits); > > > > > + vtd_paging_entry_rsvd_field[5] = > > > > VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, x86_iommu- > > > > >dt_supported); > > > > > + vtd_paging_entry_rsvd_field[6] = > > > > VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, x86_iommu- > > > > >dt_supported); > > > > > + vtd_paging_entry_rsvd_field[7] = > > > > > + VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu- > > > > >dt_supported); > > > > > vtd_paging_entry_rsvd_field[8] = > > > > >VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); > > > > > > > > Should this TM bit only affects leaves? Say, entry 1 (4K), 5 (2M), 6 (1G). [1] > > > > While this reminded me that I'm totally confused on why we have had > > > > entry 7, 8 after all... Are they really used? > > > Yes. TM bit only affects. To this array, index 1, 5,6,7 may be leaf. Will update > > a new patchset for it. > > > > Could I ask why index 7 may be leaf? > Index 7 is PDPE 1G GB leaf. I thought 1G was index 6. I've listed my understanding above [1]. Would you please double confirm? Thanks, -- Peter Xu